CML-to-CMOS Deserializer with Integrated Final-Stage Conversion
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Solution Overview
Problem
Conventional deserializers face increased power consumption and area requirements due to the need for separate CML-to-CMOS converters for each parallel data stream, especially when converting high-speed serial links to lower-speed parallel data streams, as they typically deserialize CML signals into parallel CML streams before converting to CMOS.
Innovation Solution
A CML-to-CMOS deserializer is designed with multiple stages, including a final stage that performs both one-to-two deserialization and CML-to-CMOS conversion, using level shifting circuitry and source follower-based level shifters to reduce the common mode level, allowing for the use of strongARM latches and minimizing the need for separate CML-to-CMOS converters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate CML-to-CMOS converters are used for each parallel data stream, then conversion accuracy is improved, but power consumption and area increase
Solution Approach 1:
The patent combines the CML-to-CMOS conversion function with the deserialization function into a unified circuit structure. The level shifting circuitry is integrated within the deserializer stages, allowing conversion to occur during the deserialization process rather than requiring separate converter circuits for each data stream. This merging eliminates redundant circuitry and reduces overall power consumption while maintaining conversion accuracy.
Solution Approach 2:
The deserializer circuit is designed to perform multiple functions: deserialization and CML-to-CMOS conversion. By making the deserializer universal and capable of handling both functions, the patent eliminates the need for dedicated separate converters, thereby reducing area and power consumption while maintaining the required conversion performance.
2Measurement precision
If separate CML-to-CMOS converters are used for each parallel data stream, then conversion accuracy is improved, but device area increases
Solution Approach 1:
The patent merges the CML-to-CMOS conversion function with the deserialization function into a unified circuit structure. The level shifting circuitry is integrated within the deserializer stages, allowing conversion to occur during the deserialization process rather than requiring separate converter circuits for each data stream. This merging eliminates redundant circuitry and reduces overall area while maintaining conversion accuracy.
3Device complexity
If conventional deserialization is used without integrated conversion, then circuit simplicity is maintained, but power consumption increases
Solution Approach 1:
The patent combines the CML-to-CMOS conversion function with the deserialization function into a unified circuit structure. The level shifting circuitry is integrated within the deserializer stages, allowing conversion to occur during the deserialization process rather than requiring separate converter circuits for each data stream. This merging eliminates redundant circuitry and reduces overall power consumption while maintaining circuit simplicity.
Data Source
AI summary
An example apparatus includes: a first level shifting circuit including a supply output; a first deserializer stage including a supply input, a first input, a first output, and a second output, the supply input coupled to the supply output; a second level shifting circuit including a second input and a third output, the second input coupled to the first output; and a second deserializer stage including a third input, a fourth output and a fifth output, the third input coupled to the third output.