CML Delay Cell Compensation for Linear Tuning and Constant Output Swing
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Solution Overview
Problem
Current mode logic (CML) delay cells face challenges in maintaining a linear rail-to-rail tuning range and constant output swing due to variations in load resistance and capacitance, which affect the delay cell's common mode levels and oscillation frequency, especially at the extremes of the tuning range.
Innovation Solution
The implementation of a compensation circuit with switching point optimized inverters and weighted tail current sources, which adjust the inverter switching points and supply additional currents to linearize the delay cell's time constant, allowing for a wide tuning range and constant output swing by compensating for non-linearity in the RC-load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the load capacitance is varied to change the delay cell's time constant, then the oscillation frequency or delay is adjusted, but the load resistance also changes causing the output common mode voltage to increase and the tuning range to become non-linear
Solution Approach 1:
The patent implements a feedback mechanism where the tuning voltage is fed back through a network of switches and current sources that dynamically adjust the tail current based on the tuning voltage level. This feedback loop compensates for the non-linear effects of the RC-load, maintaining a linear tuning characteristic across the entire voltage range from 0.7V to 1.0V.
Solution Approach 2:
The patent changes the operating parameters of the delay cell by dynamically adjusting the tail current magnitude based on the tuning voltage level. Through parameter changes, the invention modifies the current sources' strength in response to tuning voltage variations, thereby linearizing the overall tuning characteristic and extending the effective tuning range.
2Reliability
If the tail current is increased to compensate for decreasing load resistance, then the output common mode voltage is stabilized, but the compensation becomes ineffective at the extremes of the tuning range
Solution Approach 1:
The patent segments the compensation function into multiple discrete current sources, each activated at specific tuning voltage thresholds through the switch network. Instead of using a single continuous adjustment mechanism, the invention divides the compensation into staged segments that activate sequentially, ensuring effective compensation across the entire tuning range including the extremes where single-stage compensation fails.
Solution Approach 2:
The patent implements dynamic adjustment of the tail current by using voltage-controlled switches that continuously monitor the tuning voltage and activate appropriate current sources in real-time. This dynamic response allows the system to adapt the compensation level according to the instantaneous tuning voltage, maintaining stability throughout the full range of operation.
3Adaptability or versatility
If additional switched current sources are added to compensate for non-linearity at tuning range extremes, then the linear tuning range is extended, but the circuit complexity increases
Solution Approach 1:
The patent achieves multi-functionality by using the same tuning voltage signal for both its primary function (controlling the RC-load capacitance) and its secondary function (controlling the switch network that regulates the additional current sources). This universal use of the tuning voltage for dual purposes extends the linear tuning range without requiring separate control signals or additional complex control circuitry.
Solution Approach 2:
The compensation circuit is self-regulating because it uses the tuning voltage itself to control the activation of compensating current sources. The system serves itself by automatically detecting when compensation is needed through the tuning voltage level and activating the appropriate current sources without external intervention, thereby extending the linear range with minimal additional control complexity.
Data Source
AI summary
A current mode logic (CML) delay cell with linear rail-to-rail tuning range and constant output swing. The CML delay cell can include a tuning voltage input on a first and second transistor, contributing to a CML delay cell load, and a bias voltage input on a third transistor, as a current source I0, and a compensation circuit having switching point optimized inverters having a first plurality of transistors having a transconductance βpN and a second plurality of transistors having a transconductance βnN, wherein respective ratios of βnN/βpN determine an inverter switching point of respective switching point optimized inverters, the first and second plurality of transistors having gates coupled to the tuning voltage input of the CML delay cell, wherein the switching point optimized inverters are followed by weighted tail current sources M0N that supply additional currents to the current source I0 at a drain node of the third transistor.