Current-Mode Logic Driver With Pulse-Synced Pre-Emphasis

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Solution Overview

Problem

In semiconductor devices, signal transmission through channels with loss results in distorted waveforms due to high frequency attenuation, leading to jitter and reduced timing margins, especially in long or high-speed communications, causing inter-symbol interference and incorrect data transmission.

Innovation Solution

A transmission driver system incorporating a pulse generator and current mode logic driver that applies pre-emphasis by synchronizing load resistance values based on input signals, using NMOS and PMOS transistors and variable resistors to generate and control pulse signals, thereby adjusting the amplification gain and equalizing the signal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If pre-emphasis technique is applied to compensate for high frequency attenuation in channel loss, then signal transmission quality is improved, but current consumption increases

Engineering Contradiction:
Improvesignal transmission qualityVSAvoidcurrent consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies dynamics by making the load resistance values adjustable rather than fixed. The first and second load resistance values are dynamically changed based on pulse signals generated at falling edge time points, allowing the system to optimize pre-emphasis performance only when needed (during signal transitions) rather than continuously, thus reducing overall current consumption while maintaining signal transmission quality.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the resistance parameters dynamically. By adjusting the first and second load resistance values based on synchronized pulse signals, the system modifies the pre-emphasis ratio adaptively. This parameter change approach allows optimal compensation for high frequency attenuation during critical transitions while minimizing energy consumption during stable states.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If load resistance values are increased to enhance pre-emphasis ratio for better signal equalization, then high frequency signal transmission is improved, but power consumption increases

Engineering Contradiction:
Improvesignal equalizationVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent implements periodic action by generating pulse signals at specific falling edge time points of input signals. These periodic pulse triggers cause temporary adjustments to the load resistance values, providing pre-emphasis compensation only during signal transitions rather than continuously. This periodic modulation of resistance values achieves signal equalization while minimizing continuous power consumption.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent applies preliminary action by generating pulse signals that anticipate and prepare for signal transitions. The pulse signals are generated at falling edge time points, allowing the load resistance values to be adjusted in advance of the actual data transitions, ensuring optimal pre-emphasis is applied before high frequency components need compensation, thereby improving signal equalization efficiency.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11552656B2Current mode logic driver and transmission driver including the same
Publication Date: 2023.01.10 MAGNACHIP SEMICON LTD
  • US11552656B2 patent drawing
  • US11552656B2 patent drawing
  • US11552656B2 patent drawing

AI summary

A transmission driver includes a pulse generator and a current mode logic driver. The pulse generator is configured to generate and output a first pulse signal by synchronizing at a falling edge time point of a first input signal, and generate and output a second pulse signal by synchronizing at a falling edge time point of a second input signal. The current mode logic driver is configured to output a pre-emphasis signal to which pre-emphasis technique has been applied by changing a first load resistance value and a second load resistance value based on the first pulse signal and the second pulse signal, respectively.