CML Latch Biasing for PVT-Robust Modulo-3 Frequency Dividers

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Solution Overview

Problem

Current digital modulo-3 frequency dividers face challenges with process sensitivity, temperature sensitivity, supply voltage variations, and reduced reliability at high frequencies, limiting their maximum operating frequency and yield.

Innovation Solution

The implementation of current-mode logic (CML) latches with a differential transistor pair, cross-coupled transistor pair, and a matched set of bias transistors, along with enhanced biasing techniques such as choke resistor reverse-biasing and AC-input coupling, to reduce sensitivity to process, voltage, and temperature variations, and improve reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If standard CMOS logic is used for frequency dividers, then manufacturing simplicity is maintained, but the maximum operating frequency is limited and performance becomes unsatisfactory above 2 GHz

Engineering Contradiction:

Improvemaximum operating frequencyVSAvoidmanufacturing simplicity

Core Design Contradiction:

SpeedVSEase of manufacture

Solution Approach 1:

The patent replaces standard CMOS logic with current-mode logic (CML) circuitry, specifically using differential transistor pairs and current-steering mechanisms to achieve high-frequency operation above 2 GHz while maintaining manufacturability through standard CMOS process compatibility

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Speed

If CML frequency dividers are used to increase maximum operating frequency, then speed is improved, but sensitivity to process variation and device mismatch increases resulting in low yield

Engineering Contradiction:

Improvemaximum operating frequencyVSAvoidprocess variation sensitivity

Core Design Contradiction:

SpeedVSManufacturing precision

Solution Approach 1:

The patent employs differential signaling and balanced circuit topologies where matched transistor pairs operate in complementary fashion, causing process variations and device mismatches to affect both sides equally and thus cancel out in the differential output, improving yield while maintaining high frequency performance

Inventive Principle:

Principle #35Parameter changes

3Speed

If CML frequency dividers are used to achieve higher operating frequency, then speed is improved, but performance becomes sensitive to variations in supply voltage

Engineering Contradiction:

Improvemaximum operating frequencyVSAvoidsupply voltage sensitivity

Core Design Contradiction:

SpeedVSAdaptability or versatility

Solution Approach 1:

The patent incorporates automatic biasing circuits and current mirrors that dynamically adjust operating points based on supply voltage variations, ensuring stable differential voltage swings and consistent division ratio across supply voltage changes while maintaining high-frequency operation

Inventive Principle:

Principle #23Feedback

4Speed

If techniques are used to minimize CML block delays and increase maximum operating frequency, then speed is improved, but device reliability degrades resulting in low mean-time-to-failure

Engineering Contradiction:

Improvemaximum operating frequencyVSAvoidmean-time-to-failure

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent designs with adequate voltage headroom and includes protective clamping structures that prevent excessive voltage swings and current spikes during transient conditions, cushioning against reliability-degrading stress events while enabling aggressive delay minimization for high-frequency operation

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

5Speed

If CML frequency dividers are used to increase maximum operating frequency, then speed is improved, but the circuit fails at elevated temperatures

Engineering Contradiction:

Improvemaximum operating frequencyVSAvoidtemperature sensitivity

Core Design Contradiction:

SpeedVSTemperature

Solution Approach 1:

The patent uses differential pair configurations where temperature-induced threshold voltage shifts and mobility changes affect both transistors equally, maintaining balanced operation and stable differential output across elevated temperature ranges while preserving high-frequency performance

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS10566957B1Current-mode logic latches for a PVT-robust mod 3 frequency divider

Publication Date: 2020.02.18 AY DEE KAY LLC DBA INDIE SEMICONDUCTOR

AI summary

An illustrative digital latch includes: a differential transistor pair (“track pair”) capacitively coupled to a differential input signal to cause a differential output voltage between output nodes to track the differential input signal when a clock signal is asserted; a cross-coupled transistor pair (“latch pair”) coupled to the output nodes to latch the differential output voltage when the clock signal is de-asserted; a differential transistor pair (“clock pair”) that steers a bias current between the track pair and the latch pair; and a matched set of bias transistors that determines the bias current for the clock pair and a reference voltage on a reference voltage node, the reference voltage node being coupled to a base of each transistor in the track pair by equal bias resistances.