Quarter-Rate CML-Less Transmitter for Low-Power Pre-Emphasis
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Solution Overview
Problem
Current mode logic (CML) circuits in high-speed applications face limitations in reducing storage time and power consumption, particularly in GHz frequency range, due to the need to avoid transistor saturation and the use of passive inductors for bandwidth extension, which occupy large area and increase power consumption.
Innovation Solution
A low-power CML-less transmitter architecture that uses a main and secondary multiplexer with cascaded NMOS transistors and adjustable pseudo-PMOS loads, along with output drivers for pre-emphasis, to generate and process parallel signals and multiphase clock signals, eliminating the need for passive inductors and reducing power consumption by operating at one quarter of the line rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If CML circuits use constant current switching to achieve high-speed operation in GHz frequency range, then transmission speed is improved, but power consumption increases
Solution Approach 1:
The patent employs periodic action by operating multiplexers at one-quarter of the line rate using quarter-phase clock signals. This periodic operation allows the circuit to achieve high-speed transmission through time-interleaved parallel processing while reducing instantaneous power consumption compared to continuous CML operation. The multiplexers switch between four parallel data paths in sequence, each operating at a lower frequency.
Solution Approach 2:
The patent applies segmentation by dividing the high-speed data transmission into four parallel lower-speed channels. Each channel is processed by a separate multiplexer operating at one-quarter the line rate, with results combined through parallel processing. This segmentation allows high overall throughput while each individual circuit element operates at lower power consumption levels.
2Speed
If passive inductors are used for bandwidth extension in CML circuits, then bandwidth is improved, but area occupied increases
Solution Approach 1:
The patent replaces mechanical/passive inductor-based bandwidth extension with an electronic solution using parallel multiplexing and time-interleaved processing. Instead of relying on passive inductors to extend bandwidth, the system achieves equivalent bandwidth through four parallel channels operating at quarter-rate, combining their outputs to achieve the required overall bandwidth without large passive components.
3Speed
If passive inductors are used for bandwidth extension in CML circuits, then bandwidth is improved, but power consumption increases
Solution Approach 1:
The patent uses periodic action with quarter-phase clock signals to operate multiplexers at one-quarter line rate, achieving bandwidth extension through time-interleaved parallel processing rather than passive inductors. This approach extends effective bandwidth while consuming less power because each multiplexer operates at lower frequency with simpler circuitry, avoiding the continuous power consumption associated with inductor-based bandwidth extension.
4Speed
If transistors operate in hard saturation to increase current switching speed, then transmission speed is improved, but storage time increases
Solution Approach 1:
The patent applies periodic action by using quarter-phase clock signals to operate multiplexers at one-quarter line rate with controlled switching. This periodic operation allows transistors to switch cleanly between states without entering hard saturation, minimizing storage time effects. The time-interleaved parallel architecture compensates for the lower individual switching speed by processing four channels simultaneously, achieving overall high-speed transmission without the storage time penalties of hard saturation operation.
Data Source
AI summary
Exemplary embodiments of the present invention relate to a low-power current mode logic (CML)-less transmitter architecture. A transmitter comprises a main multiplexer configured to generate a main data signal by multiplexing parallel main data signals retimed from a retimer for time margin between parallel input data signals and a multiphase clock signals from a clock distributor, a secondary multiplexer configured to generate a post data signal by multiplexing parallel post data signals retimed from the retimer, and a plurality of output drivers configured to generate a serial data signal by summing the main data signal and the post data signal.