Dynamic Current Scaling in CML Prescaler Circuits
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Solution Overview
Problem
Conventional prescaler designs in frequency synthesizers face limitations in flexibility and performance at high frequencies due to fixed bias current and capacitive load, which can lead to degradation in system performance and yield loss.
Innovation Solution
The prescaler circuit dynamically adjusts current levels using differential amplifiers and cross-coupled latches, operating in sensing and holding states to enhance bandwidth and speed, and employs a current injection/extraction technique with small matched inverters to reduce delay and increase design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If fixed bias current is used in conventional prescaler design, then circuit simplicity is maintained, but speed and bandwidth are limited at high frequencies
Solution Approach 1:
The patent applies dynamics by transitioning from fixed bias current to dynamically adjustable bias current. The prescaler circuit uses variable bias current sources that can be adjusted based on operating conditions, allowing the circuit to adapt its speed and bandwidth characteristics. This enables the prescaler to operate reliably at higher frequencies by optimizing the bias current for different frequency ranges, directly resolving the contradiction between speed and circuit simplicity.
Solution Approach 2:
The patent changes the bias current parameter from fixed to variable. By implementing adjustable bias current sources and optimizing the bias current magnitude based on frequency of operation, the prescaler can achieve higher speeds. The design allows the bias current to be tuned to compensate for process variations and frequency dependencies, thereby improving speed without requiring complete redesign of the circuit topology.
2Power
If large device size is used to provide gain, then gain is sufficient, but capacitive load increases and slows down the circuit
Solution Approach 1:
The patent optimizes the device sizing parameters to achieve the right balance between gain and speed. By carefully selecting transistor dimensions and using multiple stages with optimized sizing, the circuit achieves sufficient gain without excessive capacitive loading. The bias current parameters are also adjusted to compensate for smaller device sizes, maintaining gain while reducing the RC time constant for faster operation.
Solution Approach 2:
The patent segments the gain function across multiple stages rather than relying on a single large device. The prescaler is divided into several amplifier stages, each providing partial gain. This segmentation allows each stage to use smaller devices with lower capacitance, while the cumulative gain across stages meets the required specification, thereby improving overall circuit speed.
3Speed
If high bias current is used to increase bandwidth, then speed improves, but power consumption increases
Solution Approach 1:
The patent implements dynamic bias current control where the bias current is adjusted based on the required bandwidth and operating frequency. The circuit can switch between different bias current levels or use variable bias sources that optimize the trade-off between speed and power consumption. This allows the prescaler to achieve high bandwidth when needed while consuming less power during normal operation, resolving the contradiction between speed and energy usage.
Data Source
AI summary
The inventive technique can dynamically adjust the current being applied within the components of a prescaler or divider. This dynamic scaling of the current can improve the speed of the divider by a factor of two or reduce the average current in half when compared to the conventional prescaler. Inverters are used to directly adjust the dynamic value of the currents. The removal of the conventional NMOS device within the conventional circuit eliminates one gate delay in the CML prescaler. Second, the inventive prescaler circuits operate under a current injection/extraction technique. A group of small matched inverters can be used to drive each current switching circuit independently within the entire prescaler as compared to a large buffer driving the entire conventional prescaler. Finally, dynamic current scaling offers the designer additional flexibility in the design trade off between the maximum current applied to the load and achieving the maximum performance.