CML Switching Circuit With Level-Shifted Control at 1.5V
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Solution Overview
Problem
Existing current mode logic (CML) circuits require a high power supply voltage, typically greater than or equal to 2.5V, due to the use of stacked bipolar junction transistors and headroom issues, leading to increased power consumption.
Innovation Solution
A circuit design that uses a combination of n-type BJTs and NMOS transistors, along with resistors and capacitors, to generate level-shifted control signals, allowing operation at a lower supply voltage of 1.5V without a stacked BJT arrangement, utilizing high pass filters to manage voltage drops and ensure adequate control signal levels for downstream CML functional circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If stacked bipolar junction transistors are used in CML circuits, then the circuit can operate reliably, but the power supply voltage must be at least 2.5V, leading to increased power consumption
Solution Approach 1:
The patent changes the voltage parameter from the conventional 2.5V or higher to 1.5V by modifying the transistor configuration. Specifically, it replaces the stacked BJT arrangement with a single BJT combined with NMOS transistors, which alters the voltage requirements and enables operation at lower supply voltage, thereby reducing power consumption while maintaining circuit functionality
Solution Approach 2:
The patent employs a composite transistor configuration combining different transistor types (BJT and NMOS) to achieve the desired low-voltage operation. The BJT provides the necessary voltage gain and control, while the NMOS transistors enable level shifting and signal conditioning, creating a hybrid structure that overcomes the limitations of pure BJT stacking
2Use of energy by moving object
If the power supply voltage is reduced to 1.5V, then power consumption decreases, but the control signal voltage levels may become insufficient for downstream CML functional circuits
Solution Approach 1:
The patent introduces an intermediary circuit stage consisting of the BJT and associated NMOS transistors that acts as a voltage buffer and level shifter. This intermediary stage receives the low-voltage control signal and transforms it into an appropriate voltage level for driving downstream CML circuits, ensuring signal adequacy while maintaining low overall power consumption
Solution Approach 2:
The patent substitutes the traditional voltage stacking mechanism (mechanical arrangement of multiple transistors in series) with an electrical signal transformation approach using the BJT-NMOS combination. This substitution allows voltage level adaptation through active circuit elements rather than passive voltage division, enabling adequate control signal levels at lower supply voltages
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the operation of CML circuits at a lower voltage supply, reducing power consumption while maintaining suitable voltage levels for controlling transistors, and allowing for the use of adjustable bias voltages to optimize circuit performance.
Implementation Method 1
a first capacitor coupled between the second current terminal of the first transistor and the first resistor
Implementation Method 2
a first resistor coupled to the first control input of the first transistor
Data Source
AI summary
A circuit includes a first transistor comprising a first control input and first and second current terminals, the first control input coupled to receive a first input control signal, and the first current terminal coupled to a first power supply node. The circuit also includes a first resistor coupled to the first control input of the first transistor, a first capacitor coupled between the second current terminal of the first transistor and the first resistor and a second transistor comprising a second control input and third and fourth current terminals, the third current terminal coupled to the first resistor and to the first capacitor.