CMOS Active Region Fabrication via Single Well Mask Doping
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Solution Overview
Problem
Conventional integrated circuit fabrication techniques for CMOS transistors are complex and costly due to the need for multiple masking steps, which hampers efficiency and yield, especially in memory circuits like DRAMs and SRAMs.
Innovation Solution
A method is introduced that reduces the complexity and cost by performing multiple doping processes through a single well mask, allowing for the formation of active regions in CMOS transistors with fewer masks, utilizing ion implantation and a gate stack structure with a dielectric layer and gate poly layer, and subsequent annealing to repair the dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional multiple masking steps are used for CMOS fabrication, then manufacturing precision is maintained, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent merges multiple doping operations (n-well, p-well, n+ source/drain, p+ source/drain) into a single masking step. The well mask is designed with regions of varying dopant concentration and composition, allowing all well formations to occur simultaneously through one ion implantation process, thereby eliminating multiple masking steps while maintaining precision
Solution Approach 2:
The well mask structure is designed to perform multiple functions simultaneously: it defines n-well regions, p-well regions, n+ source/drain regions, and p+ source/drain regions all in one step. The mask's ability to deliver different dopants through a single structure makes it a multi-functional element that replaces multiple separate masks
2Manufacturing precision
If multiple masking steps are used for CMOS fabrication, then active regions are precisely defined, but manufacturing time and cost increase
Solution Approach 1:
Multiple sequential doping steps are merged into a single simultaneous doping operation. The well mask enables all well and source/drain regions to be formed in one ion implantation step, eliminating the time required for multiple mask applications, alignments, and removals
Solution Approach 2:
The well mask is designed in advance with pre-defined regions for different dopant types and concentrations. This preliminary design allows the mask to guide multiple doping operations simultaneously without requiring sequential mask changes during the fabrication process
3Manufacturing precision
If ion implantation through gate stack is performed, then dopant distribution is precisely controlled, but dielectric layer damage occurs
Solution Approach 1:
The patent employs selective annealing parameters (temperature, time, atmosphere) to repair dielectric layer damage after ion implantation. By optimizing annealing conditions, the damaged dielectric is restored while preserving the precisely controlled dopant distribution achieved during implantation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process, reduces material and masking costs, and improves yield by allowing precise control over dopant distribution and concentration, leading to more efficient and cost-effective production of CMOS transistors.
Implementation Method 1
performing a first doping process, through the first opening of the first well mask and through the gate stack, to form a first well in the substrate beneath the first opening
Implementation Method 2
subsequent annealing to repair the dielectric layer
Data Source
AI summary
The instant disclosure discloses a method comprises receiving a substrate having a first region and a second region defined thereon and an insulating structure formed there-between; forming, extending across the first region and the second region, a gate stack including a dielectric layer and a gate poly layer formed thereon; forming a first well mask covering the second region while defining a first opening that projectively overlaps the first region to partially exposes the gate poly layer; performing a first doping process, through the first opening and the gate stack, to form a first well in the substrate beneath the first opening; and performing a second doping process through the first opening to form a first gate conductor in the gate poly layer.