CMOS Image Sensor ADC with Correlated Double Sampling Noise Reduction

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Solution Overview

Problem

Conventional CMOS image sensors face challenges in effectively reducing power noise and ramp noise, which degrade image quality due to the need for separate reference voltage generators and numerous dummy pixels, leading to reduced accuracy and incomplete noise removal.

Innovation Solution

The proposed solution involves an analog-to-digital converter with a correlated double sampling (CDS) array that uses a one-to-one matching operation between active and dummy pixels in the row direction to generate and compare sampling signals, efficiently removing power noise and ramp noise using shared circuitry and matching noise characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If a separate reference voltage generator is used to reduce power noise, then power noise reduction is improved, but device complexity increases and additional noise sources are introduced

Engineering Contradiction:
Improvepower noiseVSAvoidreference voltage generator
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent extracts the reference voltage generation function from a separate reference voltage generator and integrates it into the dummy pixel array itself. Each dummy pixel generates its own reference voltage locally, eliminating the need for a centralized reference voltage generator and its associated complexity while maintaining effective power noise reduction.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The dummy pixel array serves multiple functions: it acts as both the source of reference voltages for noise reduction and as functional dummy pixels for horizontal noise reduction. This multi-functionality eliminates the need for separate reference voltage generation circuitry while achieving both power noise and horizontal noise reduction goals.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Object-affected harmful factors

If numerous dummy pixels are used for horizontal noise reduction, then horizontal noise reduction is improved, but device complexity and area increase

Engineering Contradiction:
Improvehorizontal noiseVSAvoiddummy pixel array
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The dummy pixel array is designed to simultaneously serve as the reference voltage source for power noise reduction and as the horizontal noise reduction mechanism. By making the dummy pixels multi-functional, the patent achieves both noise reduction goals without requiring separate structures, thereby reducing overall device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If a conventional column parallel ADC scheme is used, then conversion capability is provided, but power noise and ramp noise degrade image quality

Engineering Contradiction:
Improveconversion capabilityVSAvoidimage quality degradation from noise
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent performs preliminary noise reduction by having each dummy pixel generate its reference voltage in advance, before the actual conversion process. This preliminary action of local reference voltage generation ensures that power noise is already compensated for when the conversion occurs, preventing noise degradation of image quality.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the reference voltage generation process into individual dummy pixel units, with each dummy pixel independently generating its own reference voltage. This segmentation allows for localized noise compensation without the need for a centralized reference voltage generator, thereby maintaining conversion capability while reducing noise impact on image quality.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9438830B2Analog-to-digital converter and CMOS image sensor including the same
Publication Date: 2016.09.06 SK HYNIX INC
  • US9438830B2 patent drawing
  • US9438830B2 patent drawing
  • US9438830B2 patent drawing

AI summary

A CMOS image sensor includes an active pixel array suitable for generating an active pixel signal, a dummy pixel array suitable for generating a dummy pixel signal, a row driver suitable for controlling the active pixel array and the dummy pixel array to simultaneously operate at a same column, and a correlated double sampling (CDS) array suitable for generating an active sampling signal and a dummy sampling signal, which are sampled from the active pixel signal and the dummy pixel signal by using a correlated double sampling, respectively, based on a first ramp signal and a second ramp signal, and comparing the active sampling signal with the dummy sampling signal.