CMOS Image Sensor A/D Converter Stabilization Circuit
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Solution Overview
Problem
Conventional column-parallel A/D converters face challenges in shortening the sampling period for pixel signals while maintaining low noise and accurate A/D conversion at a fast frame rate, leading to issues with linearity and increased noise due to high current consumption and capacitance values.
Innovation Solution
The proposed solution involves a modified A/D converter with a sample hold section using two capacitance elements and additional switches to apply stabilization promoting voltages, allowing for rapid stabilization of voltage levels and precise sampling, reducing the readout period without increasing chip area or noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the sampling period is shortened to increase frame rate, then productivity is improved, but measurement precision deteriorates due to insufficient voltage stabilization
Solution Approach 1:
The patent applies preliminary action by pre-charging the sampling capacitance to a predetermined voltage level before actual sampling. This preliminary voltage preparation ensures that the capacitance is ready to accurately capture the pixel signal voltage without requiring extended stabilization time, thus enabling short sampling periods while maintaining conversion accuracy.
2Speed
If high current is used to speed up voltage stabilization, then speed is improved, but use of energy worsens due to increased power consumption
Solution Approach 1:
The patent changes the voltage parameter by applying a predetermined initial voltage to the sampling capacitance before sampling. This voltage parameter change eliminates the need for high current discharge operations, achieving fast voltage stabilization without increasing power consumption, as the capacitance starts from a known voltage state rather than requiring dynamic adjustment.
3Reliability
If large capacitance values are used to maintain low noise, then reliability is improved, but volume increases leading to larger chip area
Solution Approach 1:
The patent applies preliminary action by pre-setting the sampling capacitance voltage to a predetermined level before sampling. This allows the use of smaller capacitance values while maintaining noise performance, because the initial voltage condition ensures accurate signal capture without requiring large capacitance for noise filtering, thus reducing the occupied chip area.
4Loss of time
If the sampling period is shortened, then loss of time is reduced, but manufacturing precision worsens due to insufficient voltage settling
Solution Approach 1:
The patent applies preliminary action by pre-charging the sampling capacitance to a predetermined voltage before the sampling operation. This preliminary voltage preparation ensures that the capacitance is ready to accurately capture the pixel signal voltage level without requiring extended settling time, thus enabling short sampling periods while maintaining voltage level accuracy for precise A/D conversion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables shorter sampling periods for both reset and signal levels, improving frame rate and maintaining low noise picture quality, while reducing power consumption and layout area.
Implementation Method 1
a sample hold section, which includes at least one capacitance element as a sampling capacitance element
Data Source
AI summary
The CMOS image sensor according to the present invention includes a sample hold section 3A1 for retaining an analog input signal voltage and a ramp wave signal voltage; and a comparing section 3A2 for taking an output from the sample hold section 3A1 as an input to compare it with a reverse level of itself, in which the sample hold section 3A1 applies a stabilization promoting voltage to a terminal of the sampling capacitance element so that an electric potential level of the terminal of the sampling capacitance element is promoted to become stabilized at a predetermined voltage, when the analog input signal is applied to the terminal of the sampling capacitance element.