Self-Aligned CMOS Gate Structure with Aluminum Interfacial Control

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

In the development of high-performance CMOS devices, there is a challenge in maintaining performance improvements without scaling down dimensions, particularly in achieving optimal threshold voltage control and reducing complexity in fabrication methods for CMOS structures with high-k gate dielectrics and metal gates.

Innovation Solution

The implementation of a shared gate metal layer and a p-type interfacial control layer (PICL) using a blanket disposition of an aluminum layer, which oxidizes to form a PFET interfacial control layer, allowing for simplified fabrication by using the same high-k dielectric and gate metal for both NFET and PFET devices, reducing masking steps and enabling self-alignment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If separate gate metals are used for NFET and PFET devices to achieve precise threshold voltage control, then threshold voltage precision is improved, but device complexity and fabrication complexity increase

Engineering Contradiction:

Improvethreshold voltage control precisionVSAvoidfabrication process complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent introduces an interfacial control layer between the shared gate metal and the high-k dielectric that creates local compositional differences. This layer has aluminum concentration varying from 0% to 100%, enabling different workfunctions for NFET and PFET devices using the same gate metal material, thus achieving precise threshold voltage control without separate gate metals

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent modifies the aluminum concentration parameter in the interfacial control layer to achieve different threshold voltages. By controlling the aluminum concentration between 0% and 100%, the workfunction of the gate can be tuned to provide appropriate threshold voltages for both NFET and PFET devices

Inventive Principle:

Principle #35Parameter changes

2Manufacturing precision

If traditional threshold tuning methods are used to achieve precise threshold voltage control, then threshold voltage precision is improved, but ease of manufacture deteriorates due to multiple masking steps

Engineering Contradiction:

Improvethreshold voltage control precisionVSAvoidfabrication process simplicity

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent merges the threshold tuning function into the high-k dielectric deposition process itself by forming an interfacial control layer with varying aluminum concentration. This eliminates the need for separate masking and deposition steps for threshold tuning, as the compositional gradient is created during the single high-k dielectric deposition process

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The interfacial control layer serves multiple functions simultaneously: it provides the high-k dielectric property for capacitance enhancement, creates the workfunction difference for threshold voltage control, and enables self-alignment for both NFET and PFET devices. This multi-functionality eliminates the need for separate threshold tuning processes

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Productivity

If high-k gate dielectrics are used to increase gate capacitance without scaling, then gate capacitance is improved, but manufacturing precision challenges arise in controlling threshold voltage

Engineering Contradiction:

Improvegate capacitanceVSAvoidthreshold voltage control precision

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The gate structure uses a composite material system consisting of high-k dielectric material combined with an interfacial control layer containing aluminum at varying concentrations (0%-100%). This composite structure provides both the high capacitance from the high-k dielectric and the precise threshold control from the aluminum-containing interfacial layer

Inventive Principle:

Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in optimized threshold voltages for both NFET and PFET devices, simplifies the fabrication process, and increases circuit layout density by eliminating the need for block level masks, thereby enhancing cost-effectiveness and performance.

Implementation Method 1

When the PFET device is exposed to a thermal annealing, the high-k dielectric oxidizes the Al layer, thereby turning the Al layer into a PFET interfacial control layer, modifying the gate workfunction

Methodology Applied

Scientific EffectOxidation: Oxidation

Data Source

PatentUS8030716B2Self-aligned CMOS structure with dual workfunction

Publication Date: 2011.10.04 GLOBALFOUNDRIES US INC

AI summary

A method for fabricating a CMOS structure is disclosed. The method includes the blanket disposition of a high-k gate insulator layer in an NFET device and in a PFET device, and the implementation of a gate metal layer over the NFET device. This is followed by a blanket disposition of an Al layer over both the NFET device and the PFET device. The method further involves a blanket disposition of a shared gate metal layer over the Al layer. When the PFET device is exposed to a thermal annealing, the high-k dielectric oxidizes the Al layer, thereby turning the Al layer into a PFET interfacial control layer, while in the NFET device the Al becomes a region of the metal gate.