CMOS Differential Amplifier Biasing via CMFB for IIP3 and NF
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Solution Overview
Problem
Conventional differential amplifiers in wireless communication networks face challenges in achieving high input third-order intercept point (IIP3) and low noise figure (NF) performance while maintaining a compact size, especially in CMOS structures used for low noise amplifiers and transimpedance amplifiers.
Innovation Solution
A differential amplifier design utilizing a CMOS structure with a biasing transistor coupled to a common-mode feedback (CMFB) path, where the gates of PMOS and NMOS transistors are connected to differential input nodes, and the drains are connected to differential output nodes, with a biasing current provided based on comparing the common-mode voltage to a reference voltage, enhancing IIP3 and NF performance and reducing physical size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional differential amplifiers are designed to achieve high IIP3 and low NF performance, then the amplifier size increases, but compact size is required for wireless communication networks
Solution Approach 1:
The patent merges the common-mode feedback (CMFB) circuit and biasing circuit into a single integrated structure. The CMFB circuit generates a common-mode voltage from the differential output voltages, and this same voltage is used to control the biasing transistor that provides bias current to both differential input nodes. This integration eliminates the need for separate AC coupling capacitors and reduces the overall amplifier footprint while maintaining high IIP3 and low NF performance through proper common-mode voltage control
2Device complexity
If AC coupling capacitors are used in conventional differential amplifiers, then the amplifier structure is simpler, but power consumption increases and size increases
Solution Approach 1:
The patent extracts and eliminates the AC coupling capacitors from the conventional differential amplifier structure. By using the CMFB circuit to generate and control the common-mode voltage directly at the biasing transistor, the design removes the need for large AC coupling capacitors that would otherwise be required to block DC components and set the operating point. This extraction reduces both the physical size and power consumption while maintaining the desired AC signal coupling functionality
Data Source
AI summary
Certain aspects of the present disclosure generally relate to a differential amplifier implemented using a complementary metal-oxide-semiconductor (CMOS) structure. The differential amplifier generally includes a first pair of transistors and a second pair of transistors coupled to the first pair of transistors. The gates of the first pair of transistors and gates of the second pair of transistors may be coupled to respective differential input nodes of the differential amplifier, and drains of the first pair of transistors and drains of the second pair of transistors may be coupled to respective differential output nodes of the differential amplifier. In certain aspects, the differential amplifier may include a biasing transistor having a drain coupled to a source of a transistor of the first pair of transistors and having a gate coupled to a common-mode feedback (CMFB) path of the differential amplifier.