Differential CMOS Amplifier Circuit for Low Phase Noise Output
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Solution Overview
Problem
Existing amplifier circuits experience significant phase noise degradation when converting low amplitude oscillating signals into rail-to-rail output signals, particularly when used with quartz oscillators, leading to jitter and noise issues in electronic instruments like frequency synthesizers and radio-frequency receivers.
Innovation Solution
The amplifier circuit incorporates complementary transistors connected in parallel with the diode-connected transistors of the current mirrors, which actively decrease the gate voltage and current during transition, reducing phase noise and increasing gain, while also using a fourth current mirror for power supply rejection and pseudo-differential inputs to enhance signal conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a conventional amplifier circuit is used to convert low amplitude oscillating signals into rail-to-rail output signals, then the output signal level extends over the entire supply voltage range, but significant phase noise degradation and jitter occur
Solution Approach 1:
The amplifier circuit is divided into multiple functional stages: a first operational amplifier for initial signal conditioning, a second operational amplifier for rail-to-rail output conversion, and complementary transistor pairs (PMOS/NMOS) for differential signal handling. Each stage addresses specific aspects of signal conversion while isolating noise sources, thereby reducing overall phase noise degradation
Solution Approach 2:
Complementary transistor pairs (PMOS and NMOS transistors) are introduced as intermediary elements between the input oscillating signals and the output stage. These transistors act as mediators that actively control current flow during transitions, reducing noise injection into the signal path while enabling full rail-to-rail output swing
2Stability of the object's composition
If high power consumption circuits are used to avoid phase noise degradation, then phase noise is reduced, but power consumption increases significantly
Solution Approach 1:
The circuit employs dynamic current control through complementary transistor pairs that adjust their conduction states based on the input signal phase. During transitions, the transistors actively modulate current flow to minimize noise, while during steady states, the circuit operates at lower current levels. This dynamic operation reduces average power consumption while maintaining low phase noise performance
Solution Approach 2:
The amplifier circuit changes operating parameters (current levels, transistor conduction states) dynamically based on signal conditions. By adjusting bias currents and transistor gate voltages according to the oscillation phase, the circuit achieves low phase noise during critical transitions while consuming minimal power during stable operation, avoiding the need for continuously high power consumption
3Ease of manufacture
If the amplifier circuit uses a simple structure, then ease of manufacture is improved, but phase noise degradation occurs
Solution Approach 1:
The amplifier is segmented into two main operational amplifiers with distinct functions, each implemented using standard CMOS current mirror configurations. This segmentation allows each block to be optimized independently using well-established fabrication processes, maintaining ease of manufacture while the combined architecture achieves low phase noise through coordinated operation of the stages
Solution Approach 2:
The circuit uses homogeneous CMOS transistor pairs (complementary PMOS and NMOS transistors with matched characteristics) throughout the design. This homogeneity ensures consistent noise performance across different signal conditions while maintaining compatibility with standard CMOS fabrication processes, achieving low phase noise without requiring complex or non-standard manufacturing techniques
Data Source
AI summary
The amplifier circuit (1) includes a differential pair of PMOS transistors at input (P3, P4), whose source receives a current from a current source (3). The gate of the first transistor (P3) of the pair defines a non-inverting input (XOUT) and the gate of the second transistor (P4) of the pair defines an inverting input (XIN). A drain of the first transistor (P3) of the differential pair is connected to a diode connected NMOS transistor (N2) of a first current mirror (N1, N2), and a drain of the second transistor (P4) of the differential pair is connected to a diode connected NMOS transistor (N3) of a second current mirror (N3, N4). A diode connected PMOS transistor (P2) of a third current mirror is connected to the drain of a second NMOS transistor (N4) of the second current mirror, while a drain of a second PMOS transistor (P1) of the third current mirror is connected to the drain of a second NMOS transistor (N1) of the first current mirror to define a first output (OUT1), which is inverted by a reverser (N5, P7) to supply an inverted output signal (OUT) capable of varying rail to rail. A first complementary NMOS transistor (N6) is connected in the form of a reverser with the first PMOS transistor (P3) of the differential pair. A second complementary NMOS transistor (N7) is connected in the form of a reverser with the second MOS transistor (P4) of the differential pair.