CMOS Sampling Transistor Back-Gate Bias for Lower Parasitic Capacitance
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Solution Overview
Problem
MOSFET devices face design challenges due to parasitic capacitances, particularly between the drain and substrate, and source and substrate, which introduce frequency-dependent and voltage-dependent signal corruptions, affecting circuit performance.
Innovation Solution
Applying a back gate bias voltage lower than ground for NMOS transistors or higher than VDD for PMOS transistors, combined with a bootstrap circuit to minimize parasitic capacitances and nonlinear 'on' resistance, reduces signal corruption and RC setting time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFET size is reduced to increase processing speed and reduce power consumption, then processing speed and power consumption improve, but parasitic capacitances become more significant and affect circuit performance
Solution Approach 1:
The patent applies reverse bias voltage to the back gate (substrate) to change the electrical parameters of the MOSFET. By adjusting the back gate voltage, the parasitic capacitances at the drain and source junctions are reduced, thereby mitigating their harmful effects while maintaining the benefits of smaller transistor size for high-speed operation
2Reliability
If back gate bias voltage is applied to reduce parasitic capacitances, then signal distortion is reduced, but transistor resistance increases
Solution Approach 1:
The patent optimizes the back gate bias voltage to achieve a balance between reducing parasitic capacitance and maintaining acceptable transistor resistance. By carefully selecting the reverse bias voltage level, the parasitic capacitances are sufficiently reduced to improve signal integrity while the resistance increase is kept within acceptable limits for circuit operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitances, minimizing signal distortion and maintaining circuit performance even at higher frequencies, while slightly increasing transistor resistance.
Implementation Method 1
MOSFET devices have parasitic capacitances that can be formed at the borders between the different regions of the MOSFET device. For example, parasitic capacitances can be formed between the gate and a back gate, between the source and the gate, between the source and the back gate, between the drain and the gate, and between the drain and the back gate.
Data Source
AI summary
A circuit for sampling an analog input signal may include a transistor disposed on a substrate and a sampling capacitor coupled to one of the source and the drain of the transistor. The transistor may be disposed on a substrate that is coupled to ground. A source and a drain of the transistor may be disposed in a back gate of the transistor. The analog input may be supplied to one of the source and the drain of the transistor, and the back gate may receive a back gate voltage having a value that is lower than ground.