CMOS Back Gate Delay Element Reduces Shoot-Through Current
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Solution Overview
Problem
Traditional CMOS circuits experience a brief spike in power consumption due to 'short-circuit' or 'shoot-through current' during switching, especially at high frequencies, which increases with input-voltage rise and fall time, leading to wasted power and added propagation delay.
Innovation Solution
Incorporating a first and second delay element, configured as resistor-capacitor (RC) circuits, capacitively and resistively coupled to the output and back gates of PMOS and NMOS transistors, respectively, to delay changes in threshold voltage, thereby reducing shoot-through current by controlling the timing of voltage changes across the transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the input-voltage rise and fall time is increased to reduce switching losses, then power consumption is reduced, but propagation delay increases
Solution Approach 1:
The back gate voltage is adjusted in advance before the main switching event occurs. By pre-charging or pre-discharging the back gate through the delay element, the transistor threshold voltage is prepared ahead of time, enabling faster switching with reduced shoot-through current without requiring slower input voltage transitions.
Solution Approach 2:
The invention dynamically changes the back gate voltage parameter to modulate the transistor's threshold voltage. By controlling the back gate voltage through an RC delay circuit, the threshold voltage is adjusted optimally during switching transitions, reducing shoot-through current while maintaining fast switching speeds.
2Productivity
If the switching speed is increased to improve high-frequency performance, then productivity is improved, but shoot-through current increases leading to wasted power
Solution Approach 1:
The delay element creates a controlled feedback mechanism where the back gate voltage responds to input voltage changes with a deliberate time delay. This feedback timing is optimized so that the back gate voltage changes occur at the optimal moment during switching, reducing shoot-through current while enabling fast switching speeds for high-frequency operation.
Solution Approach 2:
The back gate is prepared in advance through the delay circuit to anticipate the switching event. By pre-adjusting the threshold voltage via back gate biasing before the main switching occurs, the transistor is pre-conditioned for optimal switching performance with minimal shoot-through current even at high switching frequencies.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution substantially reduces shoot-through current, particularly in low-threshold voltage, high-voltage operation, enhancing high-speed performance while minimizing power consumption and propagation delay.
Implementation Method 1
a first delay element between the output and the first back gate... The first delay element, the first back gate insulator, and the first channel region may be a first resistor-capacitor (RC) circuit
Implementation Method 2
The first delay element, the first back gate insulator, and the first channel region may be a first resistor-capacitor (RC) circuit... the first delay element is a relative 'resistor' to the other components
Data Source
AI summary
Methods form complementary metal oxide semiconductor (CMOS) devices that include a first transistor and a complementary second transistor, and an output connected to the first transistor and the second transistor. The first transistor includes a first channel region, a first back gate, a first delay element between the output and the first back gate, and a first back gate insulator separating the first back gate from the first channel region. The second transistor includes a second channel region, a second back gate, a second delay element between the output and the second back gate, and a second back gate insulator separating the second back gate from the second channel region. The first delay element, the first back gate insulator, and the first channel region form a first resistor-capacitor (RC) circuit, and the second delay element, the second back gate insulator, and the second channel region form a second RC circuit.