CMOS Backside Drain Contact Without Isolation Wall
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Solution Overview
Problem
Conventional CMOS apparatuses face challenges in achieving efficient backside contact formation and conductivity from the power rail to Vout, leading to slower switching times due to isolation walls between nFET and pFET drains.
Innovation Solution
A self-aligned backside contact technique is implemented, where a trench is formed in the backside dielectric to remove the isolation wall and fill it with a conductive material that contacts both drain structures, enhancing electrical connection and conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If isolation walls are used between nFET and pFET drains, then device isolation is improved, but conductivity from power rail to Vout deteriorates and switching speed decreases
Solution Approach 1:
The patent removes the dielectric isolation wall between nFET and pFET drains by forming a trench that eliminates this barrier. The trench is filled with conductive material to create a backside contact that directly connects both drains to the power rail, extracting the isolation element that was limiting conductivity and switching speed.
2Ease of manufacture
If conventional frontside contact methods are used, then manufacturing process is simpler, but conductivity from power rail to Vout is insufficient
Solution Approach 1:
The patent transitions from conventional frontside contact to backside contact formation. By accessing the drains from the backside of the substrate and forming contacts in the vertical dimension through the substrate thickness, the invention achieves superior conductivity pathways that are not constrained by frontside interconnect layer limitations.
3Strength
If dielectric pillar is used to contact facing surfaces of drains, then structural support is improved, but electrical connection between drains and power rail deteriorates
Solution Approach 1:
The patent changes the material parameter of the contact structure from dielectric (insulating) to conductive material. The trench is filled with conductive material that provides both structural support and electrical connection, eliminating the need for separate dielectric pillar support while simultaneously improving electrical connectivity to the power rail.
Data Source
AI summary
A CMOS apparatus includes an n-doped field effect transistor (nFET); and a p-doped field effect transistor (pFET), each of which has a source structure and a drain structure. A common backside drain contact, which is disposed at the backside surface of the nFET and the pFET, electrically connects the nFET drain structure and the pFET drain structure to a backside interconnect layer.