CMOS Image Sensor Banding Noise Compensation via Offset Code Delay
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Solution Overview
Problem
CMOS image sensors face a trade-off between high-speed readout and low power consumption, with banding noise causing quality deterioration due to coupling noise and code delay issues in column-parallel ADC architectures.
Innovation Solution
A comparison device and CMOS image sensor design that includes a comparison block, banding value generation block, and control block to offset banding noise effects by generating an offset code delay and controlling current through the input network based on banding values, using a column-parallel ADC architecture with a single-slope ADC and correlated double sampling CDS technique.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If column-parallel ADC architecture is used to achieve high-speed readout, then readout speed is improved, but banding noise and code delay occur due to coupling noise
Solution Approach 1:
The patent applies preliminary anti-action by generating a compensation signal that opposes the banding noise before it affects the final output. The compensation signal is generated based on the relationship between the reset signal and pixel signal, and is added to the pixel signal to pre-cancel the banding noise effect, thereby reducing the harmful impact of coupling noise in the column-parallel ADC architecture.
2Speed
If column-parallel ADC architecture is used to achieve high-speed readout, then readout speed is improved, but code delay occurs due to coupling noise
Solution Approach 1:
The patent compensates for code delay by generating a compensation signal that counteracts the timing error caused by coupling noise. The compensation signal is derived from the relationship between reset and pixel signals, and is applied to correct the code delay before the final analog-to-digital conversion, thereby maintaining accurate timing relationships despite the high-speed operation.
3Use of energy by moving object
If power consumption is reduced, then energy efficiency is improved, but readout speed decreases due to trade-off constraints
Solution Approach 1:
The patent employs feedback mechanisms to optimize the balance between power consumption and readout speed. By using the relationship between reset and pixel signals to generate compensation signals, the system can maintain high-speed readout performance while using low-power operations for signal processing and noise cancellation, thereby achieving energy efficiency without sacrificing readout speed.
Data Source
AI summary
A comparison device includes a comparison block suitable for comparing a pixel signal with a ramp signal and outputting a comparison signal; a banding value generation block suitable for generating a banding value using a setting code value and an analog-digital conversion code value; and a control block suitable for controlling a current an input network of the comparison block according to the banding value outputted from the banding value generation block.