CMOS Power Amplifier Bias Circuit for Common-Mode Voltage Control
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Solution Overview
Problem
Integrating radio-frequency power amplifiers with high efficiency, high power, and high linearity into common complementary-metal-oxide semiconductor (CMOS) processes is challenging due to issues with gate direct-current bias, leading to memory effects and deteriorated linearity, particularly in power amplifiers with stacked CMOS transistors.
Innovation Solution
A bias circuit and power amplifier design that includes a feedback module, first and second bias modules, and differential amplification modules with complementary stacked transistors, utilizing operational amplifiers and resistor-capacitor circuits for precise control of output common mode voltage and frequency compensation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple MOS transistors are stacked together to share high supply voltage, then high power output is achieved, but gate DC bias control becomes critical and bandwidth decreases causing memory effects
Solution Approach 1:
The patent implements a feedback mechanism where the common-mode output voltage is fed back to the gates of the stacked transistors through resistors. This feedback loop automatically adjusts the gate voltages to maintain proper biasing conditions, eliminating the need for complex external bias control circuits and preventing memory effects caused by bandwidth limitations.
Solution Approach 2:
The stacked transistor configuration with feedback enables the circuit to self-regulate its gate bias voltages. The output voltage itself serves as the control signal, allowing the system to automatically maintain optimal operating conditions without external intervention, thereby simplifying the overall control architecture.
2Reliability
If complementarily stacked NMOS and PMOS transistors are used, then high power efficiency and linearity are achieved, but demanding requirements are imposed on DC gate bias bandwidth and common mode voltage control
Solution Approach 1:
The feedback connection from the common-mode output voltage to the gates of both NMOS and PMOS transistors creates a self-regulating system. This feedback mechanism ensures that the gate voltages automatically adjust to maintain the precise biasing conditions required for high efficiency and linearity, while simultaneously providing the necessary bandwidth without complex external control circuits.
3Power
If high supply voltage is applied for high effective output power, then power output increases, but single common CMOS transistor cannot withstand the high voltage
Solution Approach 1:
The patent divides the high-voltage blocking function across multiple transistors connected in series (stacked configuration). Each transistor in the stack handles a portion of the total supply voltage, allowing the system to achieve high power output capability while individual transistors operate within their safe voltage ratings. The feedback mechanism ensures proper voltage distribution across the stack.
Data Source
AI summary
Bias circuits for CMOS power amplifiers are provided. The bias circuit includes a feedback module, a first bias module, and a second bias module. The feedback module has a first input connected to a output common mode voltage, a second input connected to a reference voltage, and an output connected to gates of main amplification transistors in a first differential amplification module; based on a difference between the output common mode voltage and the reference voltage, the feedback module adjusts gate voltages of main amplification transistors until the output common mode voltage is equal to the reference voltage; the first bias module provides bias voltages for the first differential amplification module; the second bias module provides bias voltages for a second differential amplification module. The present disclosure adopts direct negative feedback and cascoded current mirrors, which realize accurate DC gate bias and accurate control of the output common mode voltage.