CMOS Driver Circuit Bias Decoupling for High-Voltage Operation
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Solution Overview
Problem
CMOS integrated circuits face challenges in handling high power supply voltages due to overstress across transistor terminals, leading to potential channel breakdown and gate oxide degradation, while existing solutions like cascoded pad drivers suffer from high coupling issues that slow down driving capability and increase static current.
Innovation Solution
The implementation of a CMOS circuit with complementary driver circuits that switch in opposite directions to decouple bias voltages, using additional Miller capacitors to compensate for reduced parasitic capacitance, thereby minimizing high coupling without increasing static current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a high power supply voltage is directly applied to low voltage MOS transistors, then the circuit can operate at higher voltage levels, but this causes overstress across transistor terminals leading to channel breakdown and gate oxide degradation
Solution Approach 1:
The driver circuit is divided into multiple transistor stages (first driver circuit with transistors P1, N1 and second driver circuit with transistors P2, N2) where each stage handles a portion of the voltage swing. This segmentation allows the circuit to achieve high voltage operation while individual transistors experience reduced stress.
Solution Approach 2:
Bias voltages (REFp and REFn) are introduced as intermediary voltage levels that mediate between the high supply voltage and the transistor terminal stress limits. These bias voltages control the gate terminals to ensure that voltage differences across any single transistor never exceed the maximum stress voltage Vx, even when operating at high supply voltages.
2Power
If cascoded pad driver transistor sizes are increased to drive high output loads, then the driving capability is improved, but this increases parasitic capacitance which causes high coupling and slows down the circuit
Solution Approach 1:
The second driver circuit is designed to switch in the opposite direction to the first driver circuit. When the first driver circuit switches cause coupling on bias voltages, the second driver circuit switches in reverse to decouple the bias voltages. This inverse switching action compensates for the harmful coupling effects and maintains fast switching performance.
3Power
If transistor sizes are increased to reduce coupling effects, then the driving capability is improved, but this increases static current consumption
Solution Approach 1:
The circuit employs dynamic switching where the second driver circuit adapts its switching behavior based on the state of the first driver circuit. This dynamic operation allows the circuit to maintain driving capability while minimizing static current consumption by ensuring that not all transistors are in high-current states simultaneously.
Data Source
Figure 1a~1b
Figure 1c~1d
Figure 1e~1f
AI summary
An electronic device with a CMOS circuit (CC) comprises a first driver circuit (10) having a first and second PMOS transistor (Pl, P2) and a first and second NMOS transistor (Nl, N2). The electronic device furthermore comprise a second driver circuit (20) with a third and fourth PMOS transistor (P3, P4) and a third and fourth NMOS transistor (N3, N4). The second driver circuit (20) is complementary to the first driver circuit (10) and switches in the opposite direction to the first driver circuit (10). A gate of the second and fourth PMOS transistor (P2, P4) is coupled to a first bias voltage (REPp) and a gate of the second and fourth NMOS transistor (N2, N4) is coupled to a second bias voltage (REFn). A first capacitance (C3) is coupled between the gate and the drain of the fourth PMOS transistor (P4) and a second capacitance (C4) is coupled between the gate and the drain source of the fourth NMOS transistor (N4).