CMOS and BJT Integration with Aligned Surface Heights
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Solution Overview
Problem
Current semiconductor structures face challenges in achieving optimal integration and performance of CMOS devices and bipolar junction transistors, particularly in maintaining uniform surface heights to enhance overall performance in applications like radio frequency front-end modules.
Innovation Solution
A semiconductor structure is designed with a CMOS device and a bipolar junction transistor (BJT) on a substrate, where the top surfaces of the NMOS, PMOS transistors, and BJT collector are aligned at the same height, incorporating a heterojunction BJT with specific doping regions and a high resistivity material layer to improve integration and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If CMOS devices and BJT are integrated on the same substrate, then device functionality and application versatility are improved, but surface height uniformity and manufacturing precision deteriorate
Solution Approach 1:
The patent applies local quality by providing different structural configurations for different device types on the same substrate. CMOS devices are formed with their characteristic multi-layer gate and source-drain structures, while BJT devices are formed with their specific base-collector-emitter junction structures. This allows each device type to have its optimal local structure while maintaining overall integration on the same substrate, thereby achieving both functionality and manufacturing precision.
Solution Approach 2:
The patent segments the substrate into different device regions where CMOS and BJT devices are formed separately with their respective structural requirements. By dividing the integrated circuit into distinct functional blocks with appropriate device structures, the patent enables independent optimization of each device type while maintaining overall system integration and surface height control.
2Reliability
If heterojunction BJT with specific doping regions is used, then device performance and electrical characteristics are improved, but device complexity and manufacturing steps increase
Solution Approach 1:
The patent merges the formation of heterojunction BJT doping regions with the existing CMOS device fabrication process sequence. The base-collector-emitter doping regions are introduced using implantation or diffusion steps that are integrated into the standard CMOS process flow, allowing the complex heterojunction BJT structure to be formed without adding significant manufacturing complexity or separate processing sequences.
Solution Approach 2:
The patent utilizes parameter changes in the doping process (such as doping concentration, implantation energy, and thermal diffusion conditions) to create the specific base-collector-emitter junction characteristics required for high-performance heterojunction BJT. By precisely controlling these doping parameters, the patent achieves optimal device performance while managing structural complexity through process optimization.
Data Source
AI summary
A semiconductor structure including a substrate, a complementary metal oxide semiconductor (CMOS) device, a bipolar junction transistor (BJT), and a first interconnect structure is provided. The substrate has a first side and a second side opposite to each other. The CMOS device includes an NMOS transistor and a PMOS transistor disposed on the substrate. The BJT includes a collector, a base and an emitter. The collector is disposed in the substrate. The base is disposed on the first side of the substrate. The emitter is disposed on the base. A top surface of a channel of the NMOS transistor, a top surface of a channel of the PMOS transistor and a top surface of the collector of the BJT have the same height. The first interconnect structure is electrically connected to the base at the first side of the substrate and extends to the second side of the substrate.