CMOS BJT Integration Sidewall Spacer Formation
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Solution Overview
Problem
Conventional methods for integrating CMOS and BJT devices often result in surface damage to the BJT device during the gate spacer etching process, leading to incremental current leakage due to high power reactive ion etching and over etching, which compromises production yields.
Innovation Solution
A fabrication method involving a semiconductor substrate with separate regions for CMOS and BJT devices, where a conformably deposited dielectric layer is used to form sidewall spacers on the CMOS device while leaving a thin dielectric layer on the BJT device, and subsequently removing this layer using low-power reactive ion etching or wet etching to prevent surface damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high power reactive ion etching is used to form gate spacers on CMOS devices, then the etching efficiency and spacer formation quality are improved, but surface damage occurs on BJT devices causing current leakage
Solution Approach 1:
The patent divides the semiconductor substrate into distinct first and second regions, allowing different etching conditions to be applied to different device types. The conformal dielectric layer is deposited uniformly across both regions, but selective removal in the second region preserves the dielectric layer to protect BJT surfaces during CMOS spacer etching.
Solution Approach 2:
The patent applies different treatments to different regions: the first region (CMOS) receives standard reactive ion etching for spacer formation, while the second region (BJT) has its dielectric layer preserved to prevent surface damage. This local differentiation allows each device type to be processed under optimal conditions.
2Reliability
If over etching is performed during gate spacer formation, then complete removal of oxide residues is achieved, but BJT device surfaces are damaged resulting in current leakage
Solution Approach 1:
The patent performs preliminary protection by depositing a conformal dielectric layer on the BJT device surfaces before the reactive ion etching process. This pre-deposited layer acts as a protective barrier that prevents over-etching damage to the BJT surfaces while allowing complete removal of oxide residues in the CMOS region.
Solution Approach 2:
The conformal dielectric layer serves as an intermediary protective layer between the reactive ion etching process and the BJT device surfaces. It mediates the etching process by allowing oxide removal in CMOS regions while protecting BJT regions from surface damage.
3Adaptability or versatility
If conventional integration methods are used for CMOS and BJT devices, then both devices can be formed on a single substrate, but current leakage occurs in BJT devices due to surface damage
Solution Approach 1:
The patent segments the integrated circuit into distinct processing zones, allowing CMOS and BJT devices to coexist on the same substrate without mutual interference. The selective dielectric removal creates spatial differentiation that protects BJT devices during CMOS processing.
Solution Approach 2:
The patent implements local quality control by applying different etching protection strategies to different device regions. The conformal dielectric layer is selectively retained in BJT regions to prevent surface damage and current leakage, while being removed in CMOS regions to enable proper spacer formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively prevents current leakage in the BJT device by reducing surface damage and improving production yields by controlling the etching process to minimize over-etching and power bias, as shown in the reduced initial base leakage current.
Implementation Method 1
a conformal dielectric layer is deposited on the semiconductor substrate
Implementation Method 2
an oxide layer is etched by a reactive ion etching process; the reactive ion etching process is performed by bombardment of high power reactive ions
Implementation Method 3
Source and drain doped regions and p-type well doped region, N-type doped region, and p-type heavy doped region are formed by the same ion-implanting and diffusion processes
Implementation Method 4
Source and drain doped regions and p-type well doped region, N-type doped region, and p-type heavy doped region are formed by the same ion-implanting and diffusion processes
Data Source
AI summary
Fabrication methods for integrating CMOS and BJT devices are presented. A semiconductor substrate having a first region and a second region are provided, wherein the first region includes a CMOS device, and the second region includes a BJT device. A dielectric layer is conformably deposited on the semiconductor substrate. Part of the dielectric layer is removed, thereby forming sidewall spacers on a gate structure of the CMOS device and remaining a thin dielectric layer on the BJT device. The remaining thin dielectric layer is completely removed, completing integration of the CMOS device and the BJT device.