CMOS and BJT Integration via Surface Height Alignment
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Solution Overview
Problem
Current semiconductor structures face challenges in achieving enhanced overall performance, particularly in integrating semiconductor devices like RF switches, LNAs, and power amplifiers within radio frequency front-end modules, where effective integration of CMOS and BJT devices is hindered by differences in surface heights and conductive types.
Innovation Solution
A semiconductor structure and manufacturing method that includes a substrate with a CMOS device comprising NMOS and PMOS transistors and a BJT with a collector, base, and emitter, where all top surfaces are aligned at the same height, utilizing a heterojunction bipolar transistor (HBT) configuration, and incorporating a high resistivity material layer above the devices to enhance integration and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If CMOS and BJT devices are integrated in a semiconductor structure, then the functionality and versatility of the device is improved, but the manufacturing complexity increases due to differences in surface heights and conductive types
Solution Approach 1:
The patent applies local quality by implementing different etch selectivity ratios for different regions of the semiconductor structure. Specifically, the first etch process uses a first etch selectivity ratio for the NMOS transistor channel region, while the second etch process uses a second etch selectivity ratio for the PMOS transistor channel region. This allows precise control of surface heights in different local areas to achieve the required alignment between CMOS and BJT devices.
Solution Approach 2:
The patent changes the etch selectivity ratio parameter between different etching processes. The first etch selectivity ratio is different from the second etch selectivity ratio, enabling differential removal of dielectric layers to achieve the precise surface height relationships needed for integrating devices with different conductive types while managing manufacturing complexity.
2Area of stationary object
If multiple semiconductor devices are integrated in a compact structure, then the area efficiency is improved, but the manufacturing precision requirements increase due to the need for precise surface height alignment
Solution Approach 1:
The patent implements local quality through region-specific etching processes. The first etch process targets the NMOS transistor channel region with a specific etch selectivity ratio, while the second etch process targets the PMOS transistor channel region with a different etch selectivity ratio. This localized control enables precise surface height alignment in high-density integration without requiring uniform processing across the entire wafer.
Solution Approach 2:
The patent changes the etch selectivity ratio parameter between the first and second etching processes. By adjusting this parameter differently for NMOS and PMOS regions, the patent achieves the precise surface height relationships necessary for compact device integration while maintaining manufacturability through controlled parameter variations.
Data Source
AI summary
A semiconductor structure including a substrate, a CMOS device and a BJT is provided. The substrate has a first side and a second side opposite to each other. The CMOS device includes an NMOS transistor and a PMOS transistor. The NMOS transistor includes a first N-type doped region and a second N-type doped region disposed in the substrate. The PMOS transistor includes a first P-type doped region and a second P-type doped region disposed in the substrate. The BJT includes a collector, a base and an emitter. The base is disposed on the first side of the substrate. The emitter is disposed on the base. A first metal silicide layer, a second metal silicide layer, and a third metal silicide layer are respectively located on the second side of the substrate and respectively disposed on the collector, the first N-type doped region, and the first P-type doped region.