CMOS Output Buffer Using Low-Voltage Transistors for High-Voltage Swing
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Solution Overview
Problem
The existing CMOS technology requires high voltage transistors to operate at system power supply voltage, increasing chip fabrication complexity and cost, as it necessitates the use of both low voltage and high voltage transistors on the same chip, which is costly and complex.
Innovation Solution
A high voltage CMOS output buffer is designed using only low voltage CMOS transistors, employing a series of inverter stages and voltage drop blocks to achieve a high voltage output swing, eliminating the need for high voltage transistors and reducing fabrication costs by utilizing low voltage transistors for both internal and system power supply voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If high voltage transistors are used to operate at system power supply voltage, then the output buffer can achieve high voltage output swing, but chip fabrication complexity and cost increase
Solution Approach 1:
The patent changes the operating parameters of low voltage transistors by applying controlled voltage drops across series transistors, enabling them to operate safely at higher system voltages without exceeding their maximum gate oxide voltage ratings. This allows the use of low voltage transistors instead of high voltage transistors, reducing fabrication complexity while maintaining high voltage output capability
Solution Approach 2:
The patent segments the voltage handling function across multiple low voltage transistors connected in series. Each transistor handles only a portion of the total voltage through controlled voltage drops, preventing any single transistor from exceeding its voltage rating while collectively achieving the required high voltage output swing
2Adaptability or versatility
If both low voltage and high voltage transistors are used on the same chip, then both internal and system power supply voltages can be supported, but fabrication cost increases
Solution Approach 1:
The patent makes low voltage transistors universal by designing them to handle both internal core voltage and system I/O voltage through the voltage drop mechanism. The same low voltage transistor design can be used in both low voltage logic circuits and high voltage output buffers, eliminating the need for separate high voltage transistor fabrication processes and reducing overall fabrication cost
3Ease of manufacture
If low voltage transistors are used for high voltage output, then fabrication cost is reduced, but voltage limits across gate oxide must be carefully maintained
Solution Approach 1:
The patent incorporates control logic that monitors the voltage states and dynamically adjusts the operation of series transistors to ensure that the voltage across each transistor's gate oxide remains within safe limits. This feedback control mechanism prevents overvoltage conditions while enabling cost-effective low voltage transistor usage
Solution Approach 2:
The patent applies preliminary voltage drops across certain transistors in the series chain to pre-establish safe voltage distribution before the full system voltage is applied. This preliminary action ensures that no transistor is subjected to excessive voltage stress, maintaining reliability while using low voltage transistors
Data Source
AI summary
A high voltage CMOS output buffer is constructed from low voltage CMOS transistors. The output buffer employs a series of unique CMOS inverter stages, each of which contains a switched PMOS transistor, one or more voltage drop blocks, and a switched NMOS transistor. The voltage drop blocks are composed of stacked PMOS transistors that are diode-connected—i.e., the PMOS gate terminal is connected to the PMOS drain terminal, and the PMOS body (N-well) terminal is connected to the PMOS source terminal. The diode-connected PMOS transistors reduce the voltage across the transistor gate oxide to a safe value, for all internal PMOS/NMOS transistors inside the CMOS output buffer.