CMOS Output Buffer with Low-Threshold Pair for Impedance Matching
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Solution Overview
Problem
Conventional CMOS output buffers for high-speed applications face challenges in impedance matching, leading to signal reflection and increased power consumption, which is not suitable for stringent power requirements in memory devices and other applications.
Innovation Solution
Incorporating natural complementary transistors with a lower threshold voltage in parallel with enhancement transistors in the output buffer stage, along with a time-division biasing technique using current mirrors and hold capacitors to minimize power consumption and silicon area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If enhancement MOS transistors are used for the output buffer stage, then the circuit is simple and reliable, but the output impedance is too large compared to the characteristic line impedance, causing signal reflection
Solution Approach 1:
The patent combines enhancement MOS transistors with natural MOS transistors in a parallel configuration. The enhancement MOS provides high impedance when off and low impedance when on, while the natural MOS transistor with lower threshold voltage provides better impedance matching to the transmission line. This merging of two transistor types resolves the contradiction between circuit simplicity and signal reflection prevention.
Solution Approach 2:
The patent applies different transistor characteristics to different operating conditions. The enhancement MOS transistor handles the main switching function, while the natural MOS transistor specifically addresses the impedance matching requirement at the output. This local differentiation of transistor functions allows each component to optimize its performance for its specific role.
2Object-affected harmful factors
If complementary diode-connected MOS transistors are added in parallel to each driver, then impedance matching improves, but circuit complexity and silicon area overhead increase significantly
Solution Approach 1:
The patent changes the threshold voltage parameter by using natural MOS transistors instead of standard enhancement MOS transistors for the parallel complementary pair. This parameter change allows better impedance matching without requiring the complex boosting circuits and additional capacitors that would otherwise be needed to adjust the voltage characteristics of enhancement MOS transistors.
3Power
If the output transistors operate in the saturation region, then the buffer provides high gain, but the output impedance becomes too large for proper line matching
Solution Approach 1:
The patent uses the dynamic characteristics of natural MOS transistors whose threshold voltage is less sensitive to drain-source voltage changes. This allows the transistors to maintain a more consistent output impedance across different operating points, enabling better impedance matching while preserving the ability to operate in the saturation region for high gain.
Data Source
AI summary
An output CMOS buffer includes MOS enhancement transistors and has a second complementary pair of natural or low threshold transistors, connected respectively in parallel to transistors of opposite type of conductivity of the complementary pair of enhancement MOS transistors of the final buffer stage. The gate terminals of the pair of natural or low threshold transistors are controlled by respective inverters, each supplied through a slew rate limiter of the slope of the driving current and are respectively connected between the positive supply node of the output buffer and a negative (below ground potential) node and between the common ground node of the output buffer and a positive supply node. The negative voltage and the positive voltage on the nodes are at least equal to the absolute value of the threshold voltage of the natural or low threshold transistors.