CMOS Cascode Voltage Switch for High-Voltage Stress Reduction
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Solution Overview
Problem
Current high-voltage switches in CMOS processes face limitations such as non-self-alignment, higher product costs, voltage-related stress, and limited capability to handle high input and output voltages, particularly with LDMOS devices, which are non-foundry proven and pose functional risks.
Innovation Solution
The implementation of a circuit design that includes n-type and p-type cascode stages, along with cross-coupled PMOS transistors, to generate high-voltage switching at the output terminal, enabling the propagation of voltage signals and reducing electrical stress on individual transistors, thereby supporting higher voltage ranges without relying on LDMOS.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDMOS is used in high-voltage switch, then high-voltage switching capability is achieved, but device complexity and product cost increase
Solution Approach 1:
The high-voltage switch is segmented into multiple CMOS transistors arranged in series, with each transistor handling a portion of the total voltage. This segmentation allows the use of standard CMOS technology while achieving high-voltage capability, eliminating the need for complex LDMOS devices.
Solution Approach 2:
Multiple CMOS transistors are combined in a series configuration to create a high-voltage switch. The merging of these individual transistors achieves the high-voltage capability previously requiring LDMOS, while maintaining compatibility with standard CMOS fabrication processes.
2Reliability
If LDMOS is used in high-voltage switch, then high-voltage switching is enabled, but manufacturing precision and alignment requirements worsen
Solution Approach 1:
The switch is divided into multiple standard CMOS transistors that can be manufactured using conventional alignment processes. Each transistor operates at a lower voltage portion, allowing standard manufacturing precision to suffice, unlike LDMOS which requires specialized alignment for high-voltage operation.
Solution Approach 2:
The voltage parameter is distributed across multiple transistors rather than concentrated in a single LDMOS device. This parameter change allows the use of standard CMOS manufacturing processes with typical alignment tolerances, eliminating the need for specialized high-voltage alignment techniques.
3Reliability
If LDMOS is used in high-voltage switch, then high-voltage capability is achieved, but voltage-related stress and functional risks increase
Solution Approach 1:
The high voltage is segmented across multiple transistors in series, with each transistor experiencing only a fraction of the total voltage stress. This segmentation dramatically reduces the voltage-related stress and functional risks associated with using a single LDMOS device.
Solution Approach 2:
The patent uses multiple standard CMOS transistors instead of expensive LDMOS devices. While individual CMOS transistors have lower voltage tolerance, their series arrangement achieves the required high-voltage capability with reduced stress on each component, improving overall reliability.
4Reliability
If LDMOS is used in high-voltage switch, then high-voltage switching is enabled, but additional design space is required increasing product cost
Solution Approach 1:
The high-voltage switch is segmented into multiple standard CMOS transistors that can be manufactured using existing CMOS fabrication lines. This segmentation eliminates the need for specialized LDMOS manufacturing, reducing product cost while achieving high-voltage capability.
Solution Approach 2:
The invention uses universal CMOS transistors that can serve multiple functions including high-voltage switching when arranged in series. This multi-functionality eliminates the need for specialized LDMOS devices, reducing manufacturing complexity and product cost.
Data Source
AI summary
An example of a circuit for generating high-voltage switching at an output terminal of the circuit includes a pair of n-type metal oxide semiconductor (NMOS) transistors responsive to input signals to generate a first voltage signal in a preset mode. The circuit also includes a predefined number of n-type cascode stages coupled between the output terminal and the pair of NMOS transistors to enable propagation of the first voltage signal to the output terminal. Further, the circuit includes a predefined number of p-type cascode stages coupled to the output terminal to enable propagation of the first voltage signal to an input voltage supply to the circuit. Furthermore, the circuit includes a first pair of cross-coupled p-type metal oxide semiconductor (PMOS) transistors coupled to the input voltage supply. The circuit includes a pair of PMOS transistors, coupled between the first pair of cross-coupled PMOS transistors and the p-type cascode stage.