CMOS Class AB Output Stage for 0.9V Wide-Range Operation

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Solution Overview

Problem

Existing CMOS class AB output stages are unable to operate effectively at supply voltages as low as 1 volt with acceptable linearity, output current, and stability, and often have complex circuit configurations, failing to meet the demand for low-cost, low-power operational amplifiers that can function over a wide voltage range from 0.9 to 5 volts.

Innovation Solution

A CMOS class AB output stage design featuring a first and second output transistor with specific bias voltage configurations and threshold voltage management, utilizing low threshold voltage transistors and bias circuits to stabilize quiescent current and enable operation at supply voltages as low as 0.9 volts while maintaining linearity and output current capabilities, and simplifying the circuit configuration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional class AB output stages are used, then they can operate over a wide supply voltage range, but they cannot operate effectively at supply voltages as low as 1 volt with acceptable linearity and stability

Engineering Contradiction:
Improveoperation effectiveness at low voltageVSAvoidsupply voltage range
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent changes the operating parameters of the output stage by using different transistor configurations and biasing schemes that allow operation at ultra-low voltages (0.9V-1.0V) while maintaining stability and linearity, thereby resolving the contradiction between low-voltage effectiveness and wide voltage range adaptability

Inventive Principle:
Principle #35Parameter changes

2Reliability

If prior art low voltage class AB output stages are used, then they can operate at low supply voltages, but they are characterized by poor linearity, limitation of output current, and poor stability

Engineering Contradiction:
Improveoperation at low supply voltageVSAvoidlinearity and output current stability
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent implements feedback mechanisms through the interconnected transistor configuration where the drain of each output transistor connects to the gate of the complementary transistor, creating automatic current balancing that improves linearity and output current stability while maintaining low-voltage operation

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent modifies key operating parameters including using low threshold voltage transistors, specific biasing arrangements, and optimized transistor sizing ratios to achieve poor linearity and output current limitations at low supply voltages

Inventive Principle:
Principle #35Parameter changes

3Reliability

If prior art low voltage class AB output stages are used, then they can operate at low supply voltages, but they have complex circuit configurations

Engineering Contradiction:
Improveoperation at low supply voltageVSAvoidcircuit configuration complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the biasing circuits and output stage into a single integrated configuration where the same transistors serve multiple functions, eliminating the need for separate biasing networks and reducing overall circuit complexity while maintaining low-voltage operation capability

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS7466201B1Class AB output stage and method for providing wide supply voltage range
Publication Date: 2008.12.16 TEXAS INSTRUMENTS INC
  • US7466201B1 patent drawing
  • US7466201B1 patent drawing
  • US7466201B1 patent drawing

AI summary

A class AB output stage includes first (MP) and a second (MN) output transistors having sources coupled to first (VDD) and second reference voltages, respectively, drains coupled to an output (13), and gates coupled to first (11A) and second (12A) conductors, respectively. Portions of first (IIN1) and a second (IIN2) input currents are sourced via a first input conductor (11) and a second input conductor (12), respectively, into and from sources of first (M2) and second (M4) transistors, respectively. Gates of the first (M2) and second (M4) transistors are coupled to the first and second conductors, respectively. First (VrefP) and second (VrefN) bias voltages are applied to gates of third (M1) and fourth (M3) transistors respectively, having sources coupled to the first and second input conductors, respectively, and drains coupled to the second conductor.