CMOS Class-E Power Amplifier With Double Resonance Stress Control
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Solution Overview
Problem
CMOS class-E power amplifiers face efficiency degradation and voltage stress issues due to low breakdown voltage, parasitic capacitance, and narrowband load matching, limiting their ability to deliver high output power efficiently at higher frequencies.
Innovation Solution
A double resonance circuit is implemented to control harmonic voltages and reduce transistor stress, combined with negative capacitance to compensate for surplus capacitance, allowing for higher power supply voltage and load impedance while maintaining efficiency, and a differential configuration to minimize interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the gate width is widened to reduce on-resistance and drive sufficient currents for high efficiency, then efficiency and output power are improved, but parasitic capacitance increases which limits the maximum operating frequency
Solution Approach 1:
The patent introduces negative capacitance to change the electrical parameter of the circuit by compensating for parasitic capacitance. The negative capacitance circuit is connected to the drain of the transistor to offset the surplus capacitance, thereby restoring the maximum operating frequency while maintaining the wide gate width needed for low on-resistance and high efficiency.
2Power
If the power supply voltage is increased to deliver higher output power, then output power is improved, but voltage stress on transistors increases causing breakdown
Solution Approach 1:
The patent applies harmonic control through a double resonance circuit to change the voltage waveform parameters. By controlling the harmonic voltages, the peak voltage stress on transistors is reduced while maintaining the average power delivery capability, allowing higher output power without exceeding transistor breakdown voltage.
Solution Approach 2:
The double resonance circuit creates periodic harmonic control that shapes the voltage waveform applied to transistors. This periodic action ensures that voltage peaks are limited while maintaining power delivery, preventing breakdown during high power operation cycles.
3Power
If load impedance is reduced to deliver wide range output power under low power supply voltage, then output power range is improved, but efficiency degrades and load matching becomes narrowband
Solution Approach 1:
The negative capacitance circuit changes the effective impedance parameters of the amplifier by compensating for parasitic effects. This allows the amplifier to maintain high efficiency at higher load impedances while still delivering wide output power range through the controlled impedance transformation in the load matching network.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables higher output power delivery with improved efficiency and reliability, reducing voltage stress on transistors and maintaining performance across a wider range of frequencies, while minimizing interference with other circuits.
Implementation Method 1
a first LC resonator whose one end is connected to the output of the DS and the other end to the ground as an AC equivalent circuit and a second LC resonator whose one end is connected to the input of the MS and the other end to the ground as an AC equivalent circuit
Implementation Method 2
negative capacitance which compensates for surplus capacitance from the drain of the transistor
Data Source
AI summary
The present invention includes a class-E power amplifier, comprising a driver stage (DS) including a first power amplifier with transistors, to which an input signal is inputted; a main stage (MS), including a second power amplifier with transistors, whose input is connected to the output of the DS; and a first LC resonator whose one end is connected to the output of the DS and the other end to the ground as an AC equivalent circuit and a second LC resonator whose one end is connected to the input of the MS and the other end to the ground as an AC equivalent circuit. In accordance with the present invention, as the voltage stress is reduced on the CMOS class-E power amplifier, the application of the high power supply voltage may be allowed and therefore the load impedance may be high while the same efficiency is maintained.