Multi-Moduli CMOS Clock Divider With Partial Gating for 10 GHz Stability
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Solution Overview
Problem
Clock dividers face limitations in maximum speed and stability due to process-voltage-and-temperature (PVT) variations and device aging, especially when providing multiple divide ratios, as they are bottlenecked by propagation delay through NAND gates and increased complexity.
Innovation Solution
A high-speed CMOS logic circuit with a ring oscillator comprising multiple gated inverters, where at least one inverter is partially gated with complementary control signals, allowing for selectable divide ratios and efficient operation up to 10 GHz, utilizing interconnects and select signals to achieve tri-modulus functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the driving strength of the NAND gate is increased to speed it up, then the propagation delay is reduced, but the load on previous stages increases creating a new speed bottleneck
Solution Approach 1:
The circuit is divided into multiple stages with distributed buffering. Instead of one large NAND gate, the functionality is segmented across multiple smaller gates with intermediate buffer stages, distributing the loading burden and preventing single-point bottlenecks.
Solution Approach 2:
Buffer stages are introduced as intermediary elements between the NAND gate and subsequent logic stages. These buffers act as mediators that isolate the loading effects, allowing the NAND gate to operate at high speed without directly burdening previous stages.
2Adaptability or versatility
If a single divider circuit is used for providing multiple divide ratios, then the circuit complexity increases, but the maximum speed is further reduced
Solution Approach 1:
The circuit uses dynamic control signals to enable different divide ratios (N=2,3,4,5,6) without requiring multiple static circuit implementations. The gated inverters are dynamically controlled to achieve different division ratios, maintaining speed while providing versatility.
Solution Approach 2:
A single divider circuit implementation provides multiple divide ratios through controlled gating of inverters. The same physical circuit structure serves multiple functions by selectively enabling different numbers of inverter stages based on control signals.
3Speed
If the circuit is designed for high speed operation, then the propagation delay is minimized, but stability under PVT variations and device aging deteriorates
Solution Approach 1:
The circuit employs regenerative feedback through the ring oscillator structure and synchronized clocking. The feedback mechanism continuously reinforces the oscillating signal and corrects deviations, maintaining stable divide ratios despite PVT variations and aging effects.
Solution Approach 2:
The design incorporates sufficient timing margins and uses synchronized clocking with properly timed enable signals. These preemptive measures cushion against variations by ensuring that critical transitions complete successfully even under adverse PVT conditions and aging.
Data Source
AI summary
An electronic circuit which is a high speed CMOS logic circuit to divide the frequency of an input signal is provided. The electronic circuit comprises a ring oscillator. The ring oscillator comprises a plurality of gated inverters. At least one of the gated inverters is configured to receive an oscillating signal and a control signal at two complementary inputs. The electronic circuit is configured to be partially gated such that a divide ratio is selectable. By means of clock partial gating, open loop clock buffering and avoiding slow combinatory logic in the data path, a very high speed multi-moduli clock divider is achieved.