CMOS Ring Oscillator Clock Divider for High-Speed Multi-Moduli
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Solution Overview
Problem
Clock dividers face limitations in maximum speed due to propagation delay through NAND gates, especially when providing multiple divide ratios, and struggle with stability under process-voltage-and-temperature variations and device aging.
Innovation Solution
A high-speed CMOS logic circuit with a ring oscillator comprising multiple gated inverters, where at least one inverter is partially gated with complementary control signals, allowing for selectable divide ratios and increased duty-cycle, reducing load and enhancing speed through interconnects and selective gating.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the driving strength of the NAND gate is increased to speed it up, then the propagation delay is reduced, but the load on the previous stages increases and becomes the speed bottleneck
Solution Approach 1:
The patent extracts the timing-critical function from the NAND gate and implements it using a ring oscillator with gated inverters. This removes the problematic NAND gate from the critical path while maintaining the divide-by-3 functionality, thereby eliminating the speed bottleneck caused by increasing NAND gate driving strength.
Solution Approach 2:
Instead of using the conventional approach of increasing NAND gate strength to improve speed, the patent inverts the approach by using a ring oscillator structure where the speed is determined by the oscillation frequency of the inverter chain, which can be independently optimized without affecting the load on previous stages.
2Adaptability or versatility
If a single divider circuit is used for providing multiple divide ratios, then the circuit complexity increases, but the maximum achievable speed is further reduced
Solution Approach 1:
The patent implements dynamic control of the ring oscillator by using control signals to selectively enable or disable specific inverters in the chain. This allows the same hardware structure to dynamically change its effective length and oscillation frequency, providing multiple divide ratios (div2, div3, div4) without increasing circuit complexity or reducing maximum speed.
Solution Approach 2:
The ring oscillator structure serves multiple functions: it can operate as a divide-by-2, divide-by-3, or divide-by-4 circuit depending on the control signals applied. This multi-functionality is achieved without requiring separate circuits for each divide ratio, thereby maintaining high speed while providing versatility.
3Speed
If the propagation delay through the NAND gate is reduced, then the maximum speed is improved, but the load on nodes div3_stage4 and div3_stage2 increases
Solution Approach 1:
The patent removes the NAND gate from the critical path and replaces it with a ring oscillator-based divide-by-3 circuit. This extraction eliminates the trade-off between reducing propagation delay and managing node load, as the new circuit structure distributes the loading more evenly across the stages without creating bottlenecks.
Data Source
AI summary
An electronic circuit which is a high speed CMOS logic circuit to divide the frequency of an input signal is provided. The electronic circuit comprises a ring oscillator. The ring oscillator comprises a plurality of gated inverters. At least one of the gated inverters is configured to receive an oscillating signal and a control signal at two complementary inputs. The electronic circuit is configured to be partially gated such that a divide ratio is selectable. By means of clock partial gating, open loop clock buffering and avoiding slow combinatory logic in the data path, a very high speed multi-moduli clock divider is achieved.