CMOS Clock Receiver Feedback Loops for Duty Cycle Error Correction
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Solution Overview
Problem
High-speed CMOS clock receivers face performance issues due to duty cycle errors and cross point errors, which cause phase noise, jitter, and frequency limitations, especially when dealing with differential sinusoidal clock signals that do not have a 50% duty cycle or ideal cross points.
Innovation Solution
A clock receiver system with a differential amplifier and signal conditioner that includes a duty cycle error detector and cross point error detector, generating correction signals to adjust the clock signals, ensuring rail-to-rail swings and controlled cross points through feedback loops, using current or voltage sources and inverter stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If differential sinusoidal clock signals are used to drive high-speed circuit systems, then the circuit can operate at high frequencies (100 MHz-5 GHz), but duty cycle errors and cross point errors occur causing phase noise, jitter, and frequency limit problems
Solution Approach 1:
The patent implements feedback loops that continuously monitor the duty cycle and cross point of clock signals. Duty cycle error detectors and cross point error detectors generate correction signals that are fed back to adjust the clock signal generation, thereby maintaining signal quality at high frequencies through automatic correction of detected errors
Solution Approach 2:
The patent replaces conventional mechanical or simple electronic clock generation methods with an advanced system using differential amplifiers, signal conditioners, and electronic error detection/correction circuits. This substitution enables precise control and correction of clock signals at high frequencies where traditional methods fail
2Manufacturing precision
If conventional square wave clock signals are used, then the duty cycle can be easily maintained at 50%, but the signals cannot provide rail-to-rail swings and are not suitable for high-speed operation
Solution Approach 1:
The patent transforms the clock signal parameters by converting differential sinusoidal inputs into rail-to-rail square wave outputs with controlled duty cycles. Signal conditioners and differential amplifiers adjust amplitude, frequency, and duty cycle parameters to achieve optimal signal characteristics for high-speed operation while maintaining precise duty cycle control
3Power
If rail-to-rail swing clock signals are generated, then the signal amplitude is sufficient for high-speed operation, but cross point errors occur when the input signals do not have ideal 50% duty cycles
Solution Approach 1:
The patent introduces intermediary components including differential amplifiers and signal conditioners that act as mediators between the input differential sinusoidal signals and the output rail-to-rail clock signals. These intermediaries condition the signals, correct amplitude imbalances, and ensure accurate cross points while maintaining the required signal power for high-speed operation
Data Source
AI summary
A system for correcting duty cycle errors in a clock receiver that includes a differential amplifier having inputs for a pair of differential clock signals. A duty cycle error detector has inputs for a pair of amplified clock signals and an output for a duty cycle error correction signal. A signal conditioner is also provided with the differential amplifier having an input for the duty cycle error correction signal. Furthermore, the signal conditioner adjusts the differential clock signals in response to the duty cycle error correction signal. Also, a system for correcting cross point errors in a clock receiver that includes a differential amplifier having inputs for a pair of differential clock signal. A cross point error detector has inputs for a pair of amplified clock signals and an output for a cross point error correction signal. A signal conditioner is also provided with the differential amplifier having an input for the cross point error correction signal. Furthermore, the signal conditioner adjusts the differential clock signals in response to the cross point error correction signal.