Digital CMOS Clock Generation With Phase Smoothing for High-Speed SerDes
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Solution Overview
Problem
High-speed serializer-deserializer (SerDes) circuits face challenges in robust I/Q generation with minimal mismatch and high performance phase interpolator circuits, particularly at low power and high data rates, where existing solutions are power hungry, occupy large area, and are difficult to scale with digital CMOS technologies.
Innovation Solution
A digital scalable CMOS multi-rate clock generation architecture using a wide-band injection locked ring oscillator (ILRO) for coarse phase generation, which includes a smoothing block and a pulling block to improve linearity and reduce area and power consumption, allowing for smaller receiver implementations and easier scaling with technology nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If Quadrature VCO based full-rate I/Q clock generation is used, then full-rate clock generation is achieved, but area increases and phase noise versus power consumption ratio deteriorates
Solution Approach 1:
The patent replaces the traditional Quadrature VCO (Voltage Controlled Oscillator) based full-rate I/Q clock generation with a digital CMOS based approach using phase interpolators. This substitution transitions from an analog/mixed-signal system to a fully digital system, achieving area reduction while maintaining full-rate clock generation capability. The digital phase interpolator circuit uses simple logic gates and latches instead of complex VCO circuits, directly resolving the area concern.
2Measurement precision
If current-mode logic (CML) based phase interpolator circuits are used, then high performance phase interpolation is achieved, but power consumption increases and area increases
Solution Approach 1:
The patent changes the operating parameters by using digital CMOS logic levels and timing-based phase interpolation instead of current-mode analog signals. The digital phase interpolator uses clock signals and logic gates with well-defined voltage thresholds, transitioning from analog current modes to digital voltage modes. This parameter change enables phase interpolation functionality with significantly reduced power consumption while maintaining performance through precise digital timing control.
3Measurement precision
If full-rate clock and data recovery circuits are used, then optimum recovered clock positioning is achieved, but power consumption increases
Solution Approach 1:
The patent segments the clock and data recovery function into distinct digital stages: a digital phase interpolator for coarse phase adjustment and a digital delay-locked loop for fine tuning. This segmentation allows each stage to operate efficiently in its optimal regime, with the phase interpolator handling bulk phase correction using simple digital logic and the DLL providing precise final alignment. The segmented approach reduces overall power consumption compared to a monolithic high-performance circuit.
4Adaptability or versatility
If digital CMOS implementation is used, then scalability with technology nodes is improved, but circuit performance may deteriorate at high frequencies
Solution Approach 1:
The patent replaces analog/mixed-signal circuits with fully digital CMOS circuits, substituting continuous analog operations with discrete digital timing operations. This substitution enables better scalability to advanced CMOS technology nodes where digital circuits maintain performance while analog circuits suffer from process variations. The digital phase interpolator uses logic gates and latches that scale well to smaller feature sizes, overcoming the frequency performance limitations of analog approaches in deep sub-micron technologies.
Data Source
AI summary
A high-speed clock generator device includes a phase-interpolator (PI) circuit, a smoothing block, and inverter-based low-pass filters. The PI circuit receives a multiple clock signals with different phase angles and generates an output clock signal having a correct phase angle. The smoothing block smooths the clock signals with different phase angles and generates a number of smooth clock signals featuring improved linearity. The inverter-based low-pass filters filter harmonics of the clock signals with different phase angles.