CMOS-to-CML Converter Current Compensation for Low Jitter
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Solution Overview
Problem
Existing CMOS to CML converters experience high jitter due to peak tail currents, causing instability in common mode voltage signals, which affects the converter's performance.
Innovation Solution
Incorporating current compensation devices, such as PMOS transistors or resistors, to provide an additional current path when differential transistors are turned off, thereby eliminating peak tail currents and stabilizing the common mode output voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional differential circuit is used for CMOS to CML conversion, then the converter can be implemented, but peak tail current causes high jitter and instability in common mode voltage signals
Solution Approach 1:
The patent introduces a current compensation device as an intermediary element connected in parallel with the biased transistor. This device acts as a mediator that detects and compensates for the peak tail current generated during differential transistor transitions, thereby stabilizing the common mode voltage signals without affecting the normal operation of the differential circuit.
Solution Approach 2:
The current compensation device implements a feedback mechanism by continuously monitoring the current through the biased transistor and automatically adjusting the compensation current to counteract peak tail current effects. This feedback loop ensures that common mode voltage stability is maintained dynamically during signal transitions.
2Productivity
If differential transistors are turned off simultaneously during transition phase, then the converter operates, but abrupt current change in biased transistor causes high jitter
Solution Approach 1:
The current compensation device is configured to activate before the differential transistors complete their transition, providing preliminary current compensation. This preliminary action prevents the abrupt current changes that would otherwise occur when differential transistors turn off simultaneously, thereby reducing jitter while maintaining high operation speed.
Solution Approach 2:
The patent employs beforehand cushioning by introducing a compensation current that counteracts the expected peak tail current before it fully develops. This cushioning effect smooths out current transitions and prevents the harmful abrupt changes that cause jitter, allowing the converter to operate at high speeds with improved reliability.
Data Source
AI summary
The present invention provides a low jitter CMOS to CML converter, including: a differential circuit including differential pair transistors, a pair of loads and a biased transistor, each differential transistor of the differential pair transistors having an input terminal, an output terminal and a connection terminal. With the current compensation device, an additional current path may be provided for the current of the biased transistor which is used as a constant current source when the differential transistors are turned off, so that the peak tail current in the biased transistor current may be eliminated. Thus, the problem caused by the tail current that the common mode output voltages of the converter is unstable and has a high jitter may be solved.