CMOS Image Sensor Column Noise Reduction via Parallel AD Conversion
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Solution Overview
Problem
CMOS image sensors without column amplifiers face challenges in reducing column noise without compromising image signal readout speed, leading to increased power consumption and lower frame rates.
Innovation Solution
The imaging apparatus employs a dual signal processing unit configuration for each column signal line, allowing parallel processing of pixel signals in two driving modes to reduce noise while maintaining high readout speed, utilizing a first signal processing unit for one pixel and a second unit for another, and vice versa, with overlap-reading and noise reduction operations optimized through analog-digital conversion and averaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a column amplifier is used to amplify pixel signals, then the signal-to-noise ratio is improved, but the operating voltage increases and power consumption increases
Solution Approach 1:
The pixel array is divided into multiple banks, and each bank is further divided into multiple regions. This segmentation allows different regions to be read out simultaneously through parallel column circuits, achieving signal amplification and noise reduction without requiring a single high-power column amplifier for the entire array.
Solution Approach 2:
The patent introduces a spatial dimension to the signal processing by organizing pixels into banks and regions that can be processed in parallel. This multi-dimensional organization enables simultaneous readout of multiple pixel groups, effectively distributing the amplification task across multiple lower-power column circuits rather than requiring one high-power amplifier.
2Measurement precision
If signal reading is performed multiple times and signals are added to reduce column noise, then noise reduction is achieved, but the frame rate is significantly lowered
Solution Approach 1:
The patent implements continuous noise reduction by performing addition operations on pixel signals from different regions within the same frame period. Instead of requiring multiple sequential frame readings, the parallel bank and region structure enables continuous signal accumulation and noise cancellation without interrupting the imaging flow, maintaining high frame rates while achieving effective noise reduction.
Solution Approach 2:
By segmenting the pixel array into banks and regions that can be read and processed in parallel, the system can perform multiple signal additions within a single frame period. This segmentation enables the noise reduction process to occur continuously without waiting for multiple complete frame cycles, thus preserving high frame rates.
3Use of energy by moving object
If a column amplifier is removed to reduce power consumption, then power consumption decreases, but column noise increases
Solution Approach 1:
The patent merges the functionality of multiple column circuits processing different banks and regions to collectively achieve the noise reduction that would otherwise require a single column amplifier. By combining the outputs of multiple low-power column circuits through parallel processing and signal addition, the system achieves amplifier-level noise reduction without the power consumption penalty of a single high-power amplifier.
Solution Approach 2:
The patent adds a spatial processing dimension by organizing column circuits to handle different banks and regions simultaneously. This multi-dimensional approach distributes the noise reduction task across multiple column circuits working in parallel, achieving the noise floor reduction normally associated with high-power amplification while maintaining low power consumption per circuit.
Data Source
AI summary
A plurality of analog-to-digital (AD) conversion units is provided in a column signal line connecting commonly to vertical pixel columns. A signal of one pixel is digitized by the plurality of AD conversion units and averaged to achieve noise reduction. Operations for reading signals from a plurality of pixels are performed in parallel for alleviating the decrease of the frame rate.