CMOS Image Sensor Comparator with Correlated Double Sampling
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Solution Overview
Problem
Conventional CMOS image sensors face challenges in achieving high-speed frame rates with high resolution while maintaining low power consumption, as existing analog-to-digital conversion methods increase power consumption to reduce data conversion time.
Innovation Solution
A comparator with a correlated double sampling (CDS) block that combines a comparison block, switches, and a feedback control unit to selectively use ramp-up or ramp-down signals based on pixel signal voltage levels, reducing data conversion time and power consumption by optimizing the analog-to-digital conversion process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional analog-to-digital conversion method is used, then data conversion speed is improved, but power consumption increases
Solution Approach 1:
The patent performs preliminary actions by pre-charging capacitors and pre-positioning switches in optimal states before the actual conversion cycle begins. The initialization operation prepares the comparator and CDS block in advance, allowing the main conversion to proceed faster with reduced power demand during critical operation phases.
Solution Approach 2:
The patent employs periodic action through correlated double sampling that alternates between different operational phases (initialization, signal sampling, reference sampling, and comparison). This periodic operation allows the system to reset and recharge components rhythmically, reducing average power consumption while maintaining high conversion speed through optimized duty cycles.
2Loss of time
If conventional analog-to-digital conversion method is used, then data conversion time is reduced, but power consumption increases
Solution Approach 1:
The patent segments the conversion process into distinct phases handled by separate circuit blocks: an initialization block, a CDS block for correlated double sampling, and a comparison block. Each segment operates independently with optimized timing, allowing parallel processing that reduces total conversion time while managing power consumption through phased operation rather than continuous high-power operation.
Solution Approach 2:
The patent implements dynamic operation where switches and capacitors are actively reconfigured during different phases of conversion. The feedback control unit dynamically adjusts switch states based on comparison results, enabling adaptive timing that minimizes conversion time for each specific signal while reducing unnecessary power consumption from static or redundant operations.
Data Source
AI summary
A comparison device includes; a comparison block suitable for comparing a pixel signal with a reference voltage including a ramp-up signal and a ramp-down signal; a correlated double sampling (CDS) block suitable for performing a correlated double sampling operation on the pixel signal; a first switch suitable for selectively inputting the ramp-up signal as the reference voltage based on a first switch control signal; a second switch suitable for selectively inputting the ramp-down signal as the reference voltage based on a second switch control signal; and a feedback control unit suitable for generating the first and second switch control signals based on a result of the comparison during an initialization operation.