CMOS Image Sensor Comparator Reducing Banding Noise
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Solution Overview
Problem
CMOS Image Sensors face challenges in reducing banding noise while minimizing chip area and power consumption, as existing solutions like isolation buffers increase area and power consumption and introduce gain errors.
Innovation Solution
A comparator design that changes the gain occurrence location and controls input transistors to operate in the saturation region, incorporating a gain acquisition and noise reduction block to amplify signals and reduce noise without using buffers, thereby reducing banding noise and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If isolation buffers are added to reduce banding noise, then banding noise is reduced, but chip area and power consumption increase
Solution Approach 1:
The patent removes the isolation buffer component from the system entirely. Instead of adding buffers to reduce banding noise, the invention extracts the noise source by preventing the ramp signal from directly loading the comparator input, thereby reducing chip area while maintaining noise reduction performance
Solution Approach 2:
The patent segments the signal path by introducing a separate ramp signal generation stage that does not directly interact with the comparator input. The ramp signal is generated independently and compared through a different mechanism, separating the noise-generating ramp signal path from the sensitive comparator input path
2Object-affected harmful factors
If isolation buffers are added to reduce banding noise, then banding noise is reduced, but power consumption increases
Solution Approach 1:
The patent extracts and removes the power-consuming isolation buffer component. By eliminating the buffer stage entirely and redesigning the comparison mechanism, the system reduces power consumption while achieving noise reduction through alternative means
Solution Approach 2:
The comparator circuit is designed to be self-sufficient without requiring external isolation buffers. The circuit naturally handles the ramp signal comparison through its intrinsic design, eliminating the need for additional power-consuming buffering stages
3Object-affected harmful factors
If isolation buffers are added to reduce banding noise, then banding noise is reduced, but gain errors are introduced
Solution Approach 1:
The patent removes the isolation buffer that introduces gain errors. By eliminating the buffer stage, the direct signal path is preserved, maintaining gain accuracy while achieving noise reduction through the segregated ramp signal generation approach
4Use of energy by stationary object
If column ADCs with simple structure are used, then power consumption is reduced, but chip area increases
Solution Approach 1:
The patent merges the ramp signal generation and comparison functions into a more integrated architecture. By combining these functions and optimizing the comparator design, the system achieves efficient column-parallel operation with reduced area compared to traditional column ADC approaches
Data Source
AI summary
A comparator may include: a comparison block suitable for comparing a ramp signal and a pixel signal and outputting a comparison signal; and a gain acquisition and noise reduction block suitable for amplifying the comparison signal outputted from the comparison block to acquire a gain and reduce an occurrence of noise.