CMOS Contact Layer Formation Without Hard-Mask Epitaxy Damage
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Solution Overview
Problem
The formation of epitaxial layers in semiconductor devices, such as CMOS devices, often damages structures like spacers and gate cap layers due to the need for hard masks and extensive etching and patterning processes, which complicates the manufacturability of multi-gate metal-oxide-semiconductor field-effect transistors (MOSFETs).
Innovation Solution
A method involving a pre-clean process followed by selective epitaxial deposition and patterning to form contact layers on semiconductor regions without using hard masks, allowing for the formation of epitaxial silicon-containing material within trenches in a dielectric layer, while minimizing damage to existing semiconductor structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hard masks and extensive etching/patterning processes are used to form epitaxial layers, then contact resistivity is reduced into the 10^-9 Ω·cm² regime, but damage occurs to semiconductor structures such as spacers, gate cap layers, and epitaxially grown layers
Solution Approach 1:
The patent extracts and removes the hard mask and extensive etching/patterning steps from the process flow. Instead, it uses selective epitaxial deposition that naturally forms contacts only on exposed semiconductor surfaces without requiring protective masks, thereby eliminating damage to surrounding structures while achieving low contact resistivity
Solution Approach 2:
The selective epitaxial deposition process is self-selective based on crystal orientation and surface exposure. The process automatically deposits material only where needed (on exposed semiconductor regions) without requiring external masking, and the subsequent selective removal step automatically removes deposited material from unwanted areas based on the same self-selective mechanism
2Reliability
If hard masks and extensive etching/patterning processes are used to form epitaxial layers, then contact resistivity is reduced, but the manufacturability of multi-gate MOSFETs is complicated
Solution Approach 1:
The patent removes multiple complex process steps (hard mask formation, extensive etching, multiple patterning operations) from the manufacturing flow, replacing them with a simpler selective epitaxial deposition followed by selective removal, thereby reducing process complexity while maintaining contact quality
Solution Approach 2:
The patent changes the fundamental process parameter from mechanical/chemical etching and masking to controlled epitaxial deposition. This parameter change transforms a complex multi-step process into a simpler, more direct approach that relies on material science principles rather than extensive patterning operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of contact layers with reduced damage to semiconductor structures, improving manufacturability and reducing parasitic resistance in advanced CMOS technologies by using a multi-chamber processing system for controlled epitaxial growth and selective removal processes.
Implementation Method 1
performing a first selective epitaxial deposition process to form a first contact layer on the exposed surfaces of the first semiconductor regions and a second contact layer on the exposed surface of the second semiconductor regions
Data Source
AI summary
A method of forming a contact layer in a semiconductor structure includes performing a pre-clean process on exposed surfaces of a plurality of first semiconductor regions and a plurality of second semiconductor regions formed on a substrate, wherein the exposed surfaces of the plurality of first and second semiconductor regions are each disposed within openings formed in a dielectric layer disposed over the substrate, performing a first selective epitaxial deposition process to form a first contact layer on the exposed surfaces of the first semiconductor regions and a second contact layer on the exposed surface of the second semiconductor regions, performing a patterning process to form a patterned stack, wherein the patterned stack comprises a patterned layer that comprises openings formed over the first contact layer disposed within each opening in the dielectric layer and a portion of the patterned layer that is disposed over each second contact layer disposed within each opening in the dielectric layer, and performing a selective removal process to remove the first contact layer selectively to the plurality of first semiconductor regions, the dielectric layer, and the patterned layer.