CMOS Contact Plug Epitaxial Layer for Boron Diffusion Control
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Solution Overview
Problem
In semiconductor devices with vertical memory cell arrays, the heat treatment process during memory cell formation causes boron diffusion from the CMOS circuit and contact plug, leading to increased contact resistance and the short channel effect, which deteriorates transistor characteristics.
Innovation Solution
Incorporating a doped epitaxial layer with high boron and carbon concentrations between the contact plug and the source/drain layers, which reduces boron diffusion and maintains low resistance, thereby minimizing contact resistance and the short channel effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If heat treatment is applied to form the memory cell array above the CMOS circuit, then memory cell array formation is achieved, but heat load is applied to the CMOS circuit and contact plug causing adverse influences
Solution Approach 1:
The contact plug structure and doping profile are prepared in advance before the heat treatment process. The preliminary doping configuration ensures that even when heat treatment is subsequently applied for memory cell array formation, the contact plug maintains its electrical characteristics due to the pre-established protective structure.
Solution Approach 2:
The patent creates a protective doping structure in the connection portion before heat treatment that acts as a buffer against thermal effects. This pre-configured structure cushions the CMOS circuit and contact plug from the adverse effects of subsequent heat treatment, maintaining electrical characteristics despite the thermal stress.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces contact resistance and enhances transistor performance by maintaining high boron concentration and low resistance in the epitaxial layer, improving ON-state current and heat tolerance.
Implementation Method 1
In a heat treatment process for forming the memory cell array, heat load is applied on the CMOS circuit and a contact plug, resulting in adverse influences on the electric characteristics of the CMOS and contact resistance. boron is likely to diffuse into a channel portion
Implementation Method 2
Incorporating a doped epitaxial layer with high boron and carbon concentrations between the contact plug and the source/drain layers
Data Source
AI summary
A semiconductor device in an embodiment includes a substrate and a transistor. The transistor includes a source layer, a drain layer, a gate insulation film, a gate electrode, a contact plug and a first epitaxial layer. The source layer and the drain layer are provided in surface regions of the substrate, and contain an impurity. The gate insulation film is provided on the substrate between the source layer and the drain layer. The gate electrode is provided on the gate insulation film. The contact plug is provided so as to protrude to the source layer or the drain layer downward of a surface of the substrate. The first epitaxial layer is provided between the contact plug and the source layer or drain layer, and contains both the impurity and carbon.