CMOS Contact Formation Using Selective Epitaxy Without Hard Masks
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Solution Overview
Problem
The formation and patterning of epitaxial layers in CMOS devices can damage structures such as spacers and gate cap layers due to the use of hard masks, posing challenges in manufacturability.
Innovation Solution
A method involving patterning, amorphization ion implant, selective epitaxial deposition, and recrystallization anneal processes is used to form an epitaxial layer without hard masks, protecting sensitive device components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hard mask patterning is used to form epitaxial layers, then contact resistivity is reduced, but damage occurs to spacers and gate cap layers
Solution Approach 1:
The patent removes the hard mask from the patterning process entirely, replacing it with a self-aligned approach where the epitaxial layer formation is directed by the existing trench contact geometry and selective deposition conditions, thereby eliminating the damaging effects of hard mask patterning while maintaining low contact resistivity
Solution Approach 2:
The patent introduces a sacrificial oxide layer as an intermediary that enables selective epitaxial deposition in trench contacts without requiring hard mask patterning. The oxide layer provides the necessary selectivity and protection during the epitaxial growth process, allowing low contact resistivity to be achieved without damaging spacers and gate cap layers
2Object-affected harmful factors
If selective epitaxial deposition is performed without hard masks, then damage to device structures is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent employs a self-aligned process where the trench contact geometry and deposited materials automatically define the regions for selective epitaxial deposition without requiring additional hard mask patterning steps. The process uses the structure itself to guide the deposition, reducing manufacturing complexity while protecting device structures from damage
Solution Approach 2:
The patent controls the selective epitaxial deposition through precise parameter optimization including temperature, pressure, gas flow rates, and precursor ratios. By adjusting these parameters, the process achieves high selectivity and control without requiring hard masks, thereby reducing manufacturing complexity while protecting sensitive device structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively forms an epitaxial layer without damaging existing semiconductor structures, enhancing manufacturability and reducing contact resistivity.
Implementation Method 1
performing an amorphization ion implant process to amorphize an exposed surface of the first semiconductor region within the first opening
Implementation Method 2
performing a selective epitaxial deposition process, to epitaxially form a contact layer on the exposed surface of the second semiconductor region
Implementation Method 3
performing a recrystallization anneal process to recrystallize the amorphized surface of the first semiconductor region
Data Source
AI summary
A method of forming an electrical contact in a semiconductor structure includes performing a patterning process to form a mask on a semiconductor structure, the semiconductor structure comprising a first semiconductor region, a second semiconductor region, a dielectric layer having a first opening over the first semiconductor region and a second opening over the second semiconductor region, wherein the mask covers an exposed surface of the second semiconductor region within the second opening, performing an amorphization ion implant process to amorphize an exposed surface of the first semiconductor region within the first opening, performing a removal process to remove the mask, performing a selective epitaxial deposition process, to epitaxially form a contact layer on the exposed surface of the second semiconductor region, and performing a recrystallization anneal process to recrystallize the amorphized surface of the first semiconductor region.