High-speed CMOS Current Mirror with Dynamic Gate Charging
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Solution Overview
Problem
Conventional CMOS current mirrors experience delays and require constant resistance adaptation to achieve high-speed current output, which is problematic for applications requiring rapid current changes, such as high-speed DACs and laser drivers.
Innovation Solution
The introduction of additional transistors for rapid gate charging and a damping network of transistors to reduce overshoot, along with an output cascode transistor for increased output resistance, allows for shorter rise times and reduced input voltage requirements, eliminating the need for constant resistance adaptation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional CMOS current mirror with resistor between gate terminals is used, then current mirroring function is achieved, but rise time and response time are delayed
Solution Approach 1:
The patent extracts the problematic resistor from the gate terminal connection and replaces it with a direct connection. By removing the resistive element that caused the delay, the gate terminals can be charged directly, eliminating the RC time constant limitation and achieving faster rise times and response times while maintaining the current mirroring function.
Solution Approach 2:
The patent introduces dynamic control through additional transistors that actively manage the charging of gate terminals. The first additional transistor enables rapid charging when needed, while the second additional transistor provides damping control. This dynamic approach allows the system to achieve fast response when required while maintaining stability, resolving the contradiction between speed and time delay.
2Adaptability or versatility
If ohmic resistor is used between gate terminals, then current mirroring is achieved, but resistance value must be constantly adapted to optimal value
Solution Approach 1:
The patent implements self-service by using the second additional transistor to automatically provide damping control based on the operating conditions. The transistor configuration inherently adjusts the effective resistance without requiring external adaptation circuits or control mechanisms. The system self-regulates to maintain optimal performance across different current levels, eliminating the need for constant resistance adaptation while maintaining adaptability.
3Speed
If additional transistors are added for rapid gate charging, then rise time is reduced, but device complexity increases
Solution Approach 1:
The additional transistors in the patent serve multiple functions simultaneously. The first additional transistor provides rapid gate charging for fast rise time, while also contributing to the overall current mirroring function. The second additional transistor provides damping control to prevent overshoot and ringing, while also assisting in the current transfer. This multi-functionality justifies the increased transistor count by delivering multiple performance benefits from each added component.
Solution Approach 2:
The patent incorporates feedback mechanisms where the additional transistors respond to the operating conditions of the current mirror. The second additional transistor specifically provides feedback control for damping, sensing the state of the gate charging process and adjusting its conduction accordingly. This feedback approach allows the system to achieve fast rise times while maintaining stability, making the additional transistors worthwhile by providing intelligent control rather than just adding complexity.
Data Source
AI summary
A CMOS current mirror is provided that includes a current input, an input transistor, whose conductivity path is located between the current input and a reference potential terminal, a current output, an output transistor, whose conductivity path is connected to the reference potential terminal and which supplies the current output with an output current, a gate node common for both transistors, and a supply potential terminal. The current mirror further includes a first additional transistor, whose conductivity path is located between the supply potential terminal and the gate node and whose gate terminal is connected to the current input, and a second additional transistor, whose conductivity path is located between the gate node and the reference potential terminal and whose gate terminal is connected to the gate node.