Programmable CMOS Delay Cell for Uniform Layout and Output Skew Tuning
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Solution Overview
Problem
In CMOS integrated circuits, achieving balanced rise and fall delays across various manufacturing processes, voltages, and temperatures is challenging due to the use of long-channel transistors, which leads to timing issues and potential circuit failure, especially when poly-gate Critical Dimension variations occur.
Innovation Solution
A programmable delay cell with configurable source-drain connections between stacked PMOS and NMOS transistors, allowing for adjustable delay values and output skew, maintaining a uniform cell size and layout regardless of the delay or drive strength, enabling flexible tuning of rise and fall times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If long-channel transistors are used in delay cells, then delay tuning range is improved, but manufacturing precision deteriorates due to poly-gate Critical Dimension variations
Solution Approach 1:
The patent changes the physical parameters of the transistors by using minimum channel length instead of long channel length, and adjusts the drive strength through parallel transistor configurations. This allows achieving the required delay tuning range with shorter channels that are less sensitive to poly-gate CD variations, thereby resolving the contradiction between delay tuning range and manufacturing precision
Solution Approach 2:
The patent introduces programmable delay cells with configurable delay values through control logic that can dynamically adjust the number of active delay stages. This dynamic configuration allows the system to achieve variable delay tuning without relying on long-channel transistors, reducing sensitivity to manufacturing variations while maintaining adaptability
2Adaptability or versatility
If delay cell size is increased to achieve required delay values, then delay tuning capability is improved, but device complexity increases
Solution Approach 1:
The patent divides the delay cell into multiple identical delay stages that can be selectively enabled or disabled. Each stage contributes a fixed delay amount, and by controlling which stages are active, the total delay is tuned. This segmentation allows delay tuning capability without increasing the physical size of individual stages, reducing overall device complexity
Solution Approach 2:
The patent designs a universal delay cell structure that can provide multiple delay values through a single configurable unit. The same physical infrastructure (transistors, interconnects) serves multiple delay functions by being selectively activated, eliminating the need for multiple separate delay cells of different sizes and reducing device complexity
3Measurement precision
If multiple delay cell sizes are used to achieve timing closure, then timing precision is improved, but ease of manufacture deteriorates due to redesign requirements
Solution Approach 1:
The patent implements a universal delay cell design with programmable delay values that can be configured to provide the required timing precision for different applications. This single multi-functional cell type replaces the need for multiple specialized delay cell sizes, eliminating redesign requirements and improving ease of manufacture while maintaining timing closure precision
Solution Approach 2:
The patent introduces programmable control logic that allows the delay cell to dynamically adjust its delay value based on timing requirements. This dynamic configuration capability enables a single cell design to achieve multiple timing closure scenarios without requiring physical redesign, improving ease of manufacture while maintaining precision
Data Source
AI summary
Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values and a selectable output skew value from a plurality of output skew values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values and the plurality of output skew values. The delay stage includes M parallel-coupled inverter stages of stacked PMOS transistors and stacked NMOS transistors. The stacked transistors have configurable source-drain connections between a drain and a source of each transistor, wherein the selectable delay value corresponds to a configuration of the configurable source-drain connections to adjust a delay value of each of the M inverter stages and an output skew value of the delay cell.