CMOS Delay Variation Compensation via Controlled Voltage Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
CMOS circuits experience significant delay variations due to changes in supply voltage, temperature, and process conditions, leading to performance issues and increased die area and power consumption in conventional delay lock loop designs.
Innovation Solution
A controlled voltage circuit comprising a constant current source, unity gain operational amplifier, and series-connected P-channel and N-channel MOSFET transistors, which adjusts voltage levels to compensate for variations in supply voltage, temperature, and process conditions, providing a consistent delay across different operating states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional constant voltage supply is used to reduce delay variations, then supply voltage remains constant, but CMOS delay still varies due to temperature and process variations
Solution Approach 1:
The patent employs feedback mechanisms where delay detection circuits monitor the actual delay of CMOS circuits and feed this information back to control voltage supply circuits. The control voltage is dynamically adjusted based on the detected delay, creating a closed-loop system that compensates for temperature and process variations automatically, thereby improving delay consistency without requiring complex external compensation circuits.
Solution Approach 2:
The patent implements self-service by enabling the CMOS circuit system to automatically detect and compensate for its own delay variations. The delay detection and control voltage generation are integrated within the system itself, allowing it to self-regulate performance without external intervention or complex additional compensation circuits, thus maintaining reliability while avoiding increased device complexity.
2Reliability
If common mode amplifier circuit with pull up resistor and tail current is used to control variations, then temperature, process and supply variations are controlled, but die area and power consumption increase significantly
Solution Approach 1:
The patent merges the delay detection function and control voltage generation function into an integrated control system that works closely with the delay element. By combining these functions and using the existing delay circuitry for detection purposes, the patent achieves delay stability without requiring separate common mode amplifier circuits, pull-up resistors, and tail current sources, thereby avoiding significant increases in die area and power consumption.
Solution Approach 2:
The control voltage supply circuit in the patent serves multiple functions: it provides the supply voltage to the CMOS delay circuit and simultaneously adjusts this voltage based on detected delay conditions to compensate for variations. This multi-functionality eliminates the need for separate compensation circuits, reducing overall device complexity while maintaining delay stability.
3Reliability
If local supply is generated for each delay step unit, then delay variation is reduced, but die area consumption increases
Solution Approach 1:
The patent applies segmentation by dividing the control voltage supply into multiple independently controllable voltage supply units, each corresponding to a specific delay step unit. Each unit receives a customized control voltage based on its specific delay characteristics, enabling precise compensation for delay variations across different stages without requiring physical separation or isolation, thus reducing die area consumption while maintaining delay uniformity.
Solution Approach 2:
The patent implements local quality by providing customized control voltages to different delay step units based on their specific delay characteristics. Each delay step unit receives a tailored voltage adjustment that addresses its local delay variations, achieving superior delay uniformity without requiring identical complex compensation circuits throughout, thereby optimizing die area usage.
Data Source
AI summary
Controlled voltage circuit for compensating the performance variations in integrate circuits caused by voltage supply, temperature, and process variations is proposed. The controlled voltage circuit includes several MOSFET transistors connected in series, a unity gain operational amplifier, and a constant current source with an input terminal and an output terminal. The input source terminal of the first MOSFET is connected to a constant current source and to the unity gain operational amplifier. The output terminal of the circuit is connected to the CMOS delay block. To compensate for the performance variation, the output voltage node at or before the unity gain operational amplifier is shifted higher as the operating process state is slowed down or as the temperature is increased. Conversely, the output voltage node is shifted lower as the process becomes faster or the temperature is reduced.