CMOS Delay Circuit Compensation for Voltage and Temperature Drift
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Solution Overview
Problem
Designing a delay circuit with CMOS devices that maintains a substantially constant or controllable delay over a wide range of operating conditions is challenging due to dependencies on supply voltage and temperature.
Innovation Solution
A delay circuit is implemented with multiple stages, where one stage has a direct relationship with supply voltage and an inverse relationship with temperature, while another stage has a direct relationship with temperature, allowing for a balanced and controlled delay across various environmental parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a delay circuit uses CMOS devices, then the circuit can be implemented with standard technology, but the delay varies significantly with supply voltage and temperature
Solution Approach 1:
The patent changes the parameters of the delay circuit by introducing compensation mechanisms that adjust the delay characteristics. Specifically, it uses temperature-dependent circuits to counteract temperature-induced delay variations and voltage-dependent circuits to counteract voltage-induced delay variations, thereby maintaining stable delay performance across environmental conditions while using standard CMOS technology
Solution Approach 2:
The patent implements feedback mechanisms where the delay circuit monitors its own performance deviations caused by temperature and voltage changes, and automatically compensates for these deviations. The compensation circuits are designed to provide opposing delay changes that cancel out the environmental effects, creating a self-regulating system that maintains constant delay
2Reliability
If the delay circuit compensates for temperature variations, then delay stability improves, but circuit complexity increases
Solution Approach 1:
The patent segments the delay circuit into multiple independent delay elements, each with specific temperature compensation characteristics. By dividing the overall delay function into separate stages with different temperature coefficients, the circuit achieves temperature compensation without requiring a completely complex redesign, as each segment can be optimized independently
Solution Approach 2:
The patent merges the delay function with temperature compensation functions by integrating compensation circuits directly into the delay path. Rather than adding separate compensation modules, the design combines multiple delay circuits with opposing temperature dependencies into a unified structure that simultaneously provides delay and temperature compensation
3Reliability
If the delay circuit compensates for voltage variations, then delay stability improves, but circuit complexity increases
Solution Approach 1:
The patent changes the voltage-dependent parameters of the delay circuit by introducing compensation mechanisms that adjust the delay characteristics in response to voltage variations. The compensation circuits are designed to provide opposing delay changes that cancel out the voltage effects, maintaining stable delay performance across voltage conditions
4Reliability
If multiple delay circuits are combined for compensation, then delay control improves, but the circuit occupies more area
Solution Approach 1:
The patent merges multiple delay circuits into a compact integrated structure where compensation circuits are combined with the main delay path. By integrating rather than placing components separately, the design achieves effective delay control through multiple circuits while minimizing the total area occupied by sharing common elements and using compact layouts
Data Source
AI summary
A delay circuit with multiple dependencies on various environmental parameters is disclosed. The delay circuit is configured to receive an input signal. The delay circuit includes a first circuit configured to generate a first amount of delay, wherein the first amount of delay has a direct relationship to a first environmental parameter. The delay circuit also includes a second circuit configured to generate a second amount of delay such that the second amount of delay has an inverse relationship to a second environmental parameter. The delay circuit is configured to generate a delayed output signal based on the first and second amounts of delay generated by the first and second circuits.