CMOS Delay Bias Circuit for PVT-Stable Time Generation
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Solution Overview
Problem
CMOS delay circuits are susceptible to process, voltage, and temperature (PVT) variations, leading to unstable time delays, which conventional voltage or current regulation techniques cannot effectively address, especially in programmable delay lines and digital RF phase shifters, requiring closed-loop correction and long startup/settling times.
Innovation Solution
A novel bias generator using an operational amplifier and on-chip resistive module, coupled with switched capacitor resistors, generates PVT-stable bias signals for CMOS delay circuits, ensuring time delay stability by controlling the ratio of load capacitance to switch capacitance, independent of supply voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional voltage or current regulation techniques are used to stabilize time delay, then some level of control is achieved, but the system requires closed-loop correction and experiences long startup/settling times
Solution Approach 1:
The patent pre-charges capacitive loads to predetermined voltage levels before signal transitions are needed. This preliminary action ensures that when a transition is required, the capacitors are already charged to the correct voltage, eliminating the need for long settling times and removing the requirement for closed-loop correction mechanisms.
Solution Approach 2:
The patent replaces conventional voltage or current regulation techniques (which require continuous feedback and adjustment) with a capacitor-based voltage generation system. This substitution uses directly controlled capacitor voltage levels that can be set to predetermined values, providing stable time delays without the need for ongoing regulation mechanisms.
2Ease of manufacture
If CMOS delay circuits are used to generate time delays, then the circuit is compact and integrates well, but the time delay becomes susceptible to process, voltage, and temperature variations
Solution Approach 1:
The patent changes the operating parameters of the CMOS delay circuit by using predetermined capacitor voltage levels that are specifically designed to be insensitive to PVT variations. By setting capacitors to specific voltage levels (first, second, third voltage levels), the system achieves stable time delays that maintain their characteristics across process, voltage, and temperature changes while retaining CMOS integration benefits.
Data Source
Figure 1A~1B
Figure 1C
Figure 2
AI summary
A method of generating precise and PVT-stable time delay or frequency using CMOS circuits is disclosed. In some implementations, the method includes providing a reference voltage using a resistive module at a positive input terminal of an operational amplifier, coupling gates of a pair of p-type metal oxide semiconductor (pMOS) transistors and a compensation capacitor to an output terminal of the operational amplifier to generate a first bias signal, and coupling a pair of n-type metal oxide semiconductor (nMOS) transistors to a negative terminal of the operational amplifier to generate a second bias signal at the negative terminal, wherein the pair of nMOS transistors is substantially the same as a pair of nMOS transistors in the CMOS delay circuit.