CMOS Depth Sensor Element Fringing Electric Field Carrier Transfer
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Solution Overview
Problem
Conventional CMOS depth sensor elements have slow sensing response speeds, limiting their ability to support high-speed image sensor development.
Innovation Solution
The CMOS depth sensor element incorporates a semiconductor structure with a photogate and transfer gates connected to floating doped regions of opposite polarity, establishing a fringing electric field to accelerate the transfer of majority carriers, eliminating the need for a first doped region in the transfer transistor and enhancing signal output speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional transfer transistor structure with a first doped region is used, then the device can transfer majority carriers, but the sensing response speed is slow
Solution Approach 1:
The patent removes the first doped region from the transfer transistor structure. By extracting this unnecessary component, the patent eliminates the PN junction barrier that prevented direct connection between the photogate and the transmitting node, thereby enabling direct carrier transfer and significantly improving sensing response speed while simplifying the device structure
Solution Approach 2:
The patent segments the transfer transistor into distinct functional regions: the photogate element, the transfer gate, and the floating doped region serving as the transmitting node. This segmentation allows each component to perform its specific function optimally without the interference of the conventional first doped region, improving overall carrier transfer efficiency
2Speed
If majority carriers are transferred by diffusion through a PN junction, then carrier transfer can occur, but the transferring speed is slow
Solution Approach 1:
The patent replaces the diffusion-based carrier transfer mechanism (which relies on random thermal motion through a PN junction) with an electric field-driven drift mechanism. By directly connecting the photogate to the floating doped region, carriers are accelerated by the electric field formed during the transfer phase, significantly increasing transfer speed
Solution Approach 2:
The patent applies a transfer signal to the transfer gate in advance to create a strong electric field before carrier transfer is needed. This preliminary action prepares the electric field configuration to rapidly accelerate carriers from the photogate to the transmitting node, enabling fast response
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly increases the output speed of sensing signals by utilizing a fringing electric field effect, improving the responsiveness of the CMOS depth sensor element beyond conventional limitations.
Implementation Method 1
establishing a fringing electric field to accelerate the transfer of majority carriers
Implementation Method 2
When light is emitted to the photosensitive region A, the photogate element 70 is excited to generate majority carriers
Data Source
AI summary
A complementary metal-oxide-semiconductor depth sensor element comprises a photogate formed in a photosensitive area on a substrate. A first transfer gate and a second transfer gate are formed respectively on two sides of the photogate in intervals. A first floating doped area and a second floating doped area are formed respectively on the outer sides of the first transfer gate and the second transfer gate. The first and second floating doped regions have dopants of a first polarity and the semiconductor area has dopants of a second polarity opposite to the first polarity. Since the photogate and at least parts of the first and second transfer gates connect to the same semiconductor area and no other dopants of polarity opposite to the second polarity. Therefore, the majority carriers from the photogate excited by lights drift, but not diffuse, to transfer to the first and second transfer gates.