CMOS Gate Dielectric Dipole Patterning for Threshold Voltage Tuning
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Solution Overview
Problem
Existing CMOS devices, particularly multi-gate devices like FinFET and gate-all-around devices, face challenges in tuning threshold voltages effectively due to their small size, limiting performance enhancement and power consumption optimization.
Innovation Solution
Incorporating different types of dipole materials into the gate dielectric layers of n-type and p-type MOSFETs, along with the use of various work function metals, to flexibly tune threshold voltages without increasing device dimensions, applicable to both multi-gate and planar CMOS devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If multi-gate devices are scaled down to smaller dimensions, then device density and integration are improved, but threshold voltage tuning capability deteriorates due to limited room for work function metal variations
Solution Approach 1:
The patent introduces dipole patterns in the gate dielectric layer, adding a vertical/dielectric dimension for threshold voltage control. Instead of relying solely on lateral work function metal variations, the invention uses dipole moments oriented perpendicular to the channel, enabling Vt tuning through dielectric layer modifications rather than metal layer variations.
Solution Approach 2:
The patent changes the physical and chemical parameters of the gate dielectric layer by incorporating dipole materials with specific dipole moments. By selecting dipole materials with different dipole moment magnitudes and orientations, the threshold voltage can be precisely tuned without changing the device geometry or work function metal composition.
2Productivity
If multiple threshold voltages are provided for different transistors, then performance and power consumption are optimized, but device complexity and fabrication process complexity increase
Solution Approach 1:
The patent merges the threshold voltage tuning function into the gate dielectric layer formation process. By incorporating dipole materials during the dielectric deposition sequence and using patterned dipole layers combined with thermal annealing to drive dipole elements into the dielectric, multiple Vt options are achieved within a unified fabrication flow rather than requiring separate processing streams for different Vt devices.
Solution Approach 2:
The patent performs preliminary patterning of dipole layers before final gate dielectric formation. Dipole patterns are formed in the gate dielectric layer prior to completing the gate structure, allowing subsequent processing steps to proceed uniformly across all devices while the pre-established dipole patterns provide the desired Vt differentiation.
3Adaptability or versatility
If dipole patterns are formed in gate dielectric layers, then threshold voltage tuning is achieved, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses patterned dipole layers as intermediary structures that are subsequently processed to form the final dipole patterns in the gate dielectric. The dipole layers serve as a mask and source material, allowing indirect formation of dipole patterns through thermal annealing-driven diffusion rather than requiring direct high-precision patterning of the dipole elements themselves into the finished dielectric structure.
Solution Approach 2:
The patent replaces mechanical/physical patterning methods with thermally-driven diffusion processes. Instead of using lithography and etching to directly pattern dipole elements into the gate dielectric, the invention uses thermal annealing to drive dipole elements from patterned dipole layers into the dielectric matrix, substituting high-precision mechanical patterning with a more tolerant thermal diffusion process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the reduction of threshold voltages for both n-type and p-type transistors, providing standard and reduced threshold voltage options, improving device performance and power efficiency while maintaining device size.
Implementation Method 1
annealing the structure such that elements of the first dipole pattern are driven into the first gate dielectric layer and elements of the second dipole pattern are driven into the second gate dielectric layer
Data Source
AI summary
A method includes providing a structure having a substrate, first and second channel layers over the substrate, and first and second gate dielectric layers over the first and the second channel layers respectively. The method further includes forming a first dipole pattern over the first gate dielectric layer, the first dipole pattern having a first dipole material that is of a first conductivity type; forming a second dipole pattern over the second gate dielectric layer, the second dipole pattern having a second dipole material that is of a second conductivity type opposite to the first conductivity type; and annealing the structure such that elements of the first dipole pattern are driven into the first gate dielectric layer and elements of the second dipole pattern are driven into the second gate dielectric layer.