CMOS Fractional Divider With Four-Phase Interleaving for Low Noise
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Solution Overview
Problem
Conventional CMOS logic technology faces speed limitations above 5 GHz, leading to amplified quantization noise in Fractional-N mode phase-locked loop circuits due to high speed dividers, which complicates calibration and increases power and area, making it difficult to implement multi-GHz fully synthesizable CMOS fractional dividers effectively.
Innovation Solution
A multi-GHz fully synthesizable CMOS fractional divider is implemented using CMOS logic with a fixed divide-by-4 high-speed divider, interleaving four phase clock signals to reduce quantization noise and operate at a full rate, avoiding the need for complicated calibration schemes and current-mode logic, thus reducing design complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high speed divider is used in Fractional-N mode PLL circuit for frequencies above 5 GHz, then the output frequency can be achieved, but quantization noise is amplified by the divide ratio
Solution Approach 1:
The high speed divider is segmented into multiple parallel dividers operating at lower speeds. Instead of using a single high-speed divider with high divide ratio, the patent employs multiple dividers that process different portions of the frequency division task, thereby reducing the divide ratio of each individual divider and minimizing quantization noise amplification while maintaining the required output frequency.
Solution Approach 2:
An intermediary frequency stage is introduced between the VCO output and the final division stage. The patent uses a intermediate frequency generator to convert the VCO output to an intermediate frequency, which is then divided down. This intermediary approach allows the system to achieve high output frequencies without requiring a single high-speed divider with high divide ratio, thus reducing quantization noise.
2Object-generated harmful factors
If the divide ratio of the high speed divider is reduced to reduce quantization noise, then quantization noise is reduced, but the output frequency from the high speed divider is limited due to CMOS technology limitations
Solution Approach 1:
The frequency division function is segmented across multiple divider stages operating in parallel. Each divider operates at a reduced divide ratio and lower speed requirement, avoiding the need for a single high-speed divider with high divide ratio. This segmentation enables the system to reduce quantization noise while still achieving the required output frequency through combinatorial logic.
Solution Approach 2:
The patent transitions from a single-dimensional frequency division approach to a multi-dimensional approach by introducing multiple parallel divider paths. Instead of increasing the speed of a single divider, the system uses multiple dividers operating at moderate speeds with different divide ratios, combining their outputs to achieve the desired high output frequency while keeping individual divider speeds within CMOS capabilities.
3Speed
If complicated calibration schemes and current-mode logic are implemented to resolve CMOS limitations, then multi-GHz operation is achieved, but design complexity, power consumption and area increase
Solution Approach 1:
The patent replaces complex, power-hungry current-mode logic circuits with simpler CMOS logic circuits that use standard voltage-mode operation. Instead of implementing complicated calibration schemes, the invention uses straightforward digital control logic and combinational logic to achieve multi-GHz operation, significantly reducing design complexity, power consumption, and circuit area while maintaining the required performance.
Data Source
AI summary
An apparatus includes a fractional divider and a modulator circuit. The fractional divider circuit may be configured to generate a feedback clock signal in response to a selection signal, a divided clock signal and an output clock signal. The modulator circuit may be configured to generate the selection signal in response to the feedback clock signal. The fractional divider may generate four phase clock signals from the divided clock signal. The four phase clock signals may be interleaved by the fractional divider circuit to select one of the four phase clock signals as the feedback clock signal. The fractional divider operates at a divide-by-4 clock speed. The selection signal may be synchronized in response to the divided clock signal to generate the feedback clock signal. The fractional divider circuit may be implemented using CMOS logic.