CMOS Fractional Divider Using Four-Phase Interleaving for Low Noise
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Solution Overview
Problem
Conventional CMOS logic technology faces limitations in implementing multi-GHz fully synthesizable fractional dividers, leading to increased design complexity, power consumption, and area due to the need for high-speed dividers and complicated calibration schemes, which amplify quantization noise and limit output frequency.
Innovation Solution
A multi-GHz fully synthesizable CMOS fractional divider is implemented using a fixed divide-by-4 high-speed divider, interleaving four phase clock signals to reduce quantization noise and operate at a full rate, thereby avoiding the use of complicated calibration schemes and current-mode logic, while maintaining flexibility in switching technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high-speed divider is used to operate above 5 GHz, then the output frequency can be increased, but quantization noise is amplified by the divide ratio
Solution Approach 1:
The divider is segmented into a high-speed divider (fixed divide-by-4) and a slow divider (wide range), where each operates at optimal speeds for their function. The high-speed divider operates at full rate to generate intermediate frequencies, while the slow divider handles the remaining division at lower speeds, preventing quantization noise amplification.
Solution Approach 2:
Four phase clock signals are generated periodically and interleaved in sequence to select the feedback clock signal. This periodic interleaving allows the system to operate at full rate while distributing the division across multiple phases, reducing quantization noise compared to continuous high-speed division.
2Object-generated harmful factors
If the divide ratio of the high-speed divider is reduced to reduce quantization noise, then the output frequency from the high-speed divider is limited due to CMOS technology limitations
Solution Approach 1:
The division function is segmented between two dividers: the high-speed divider uses a fixed divide-by-4 ratio to operate at maximum frequency, while the slow divider provides the remaining wide-range division. This segmentation allows each divider to operate within its optimal frequency range without compromising overall output frequency or noise performance.
Solution Approach 2:
The high-speed divider acts as an intermediary stage that converts the VCO output to an intermediate frequency suitable for the slow divider. This intermediate stage enables the system to achieve high output frequencies while keeping the final division ratio low, thus reducing quantization noise.
3Speed
If complicated calibration schemes and current-mode logic are implemented to resolve CMOS limitations, then the design complexity, power consumption, and area increase
Solution Approach 1:
The invention uses standard CMOS logic gates instead of complex current-mode logic or calibration schemes. By relying on simple, well-understood CMOS components with fixed timing characteristics, the design avoids the need for complicated calibration circuitry while achieving multi-GHz operation.
Solution Approach 2:
The design changes the operating parameters by using fixed divide-by-4 and wide-range slow division ratios that are optimized for CMOS technology. This parameter optimization allows the system to achieve high frequencies without requiring dynamic calibration or complex control logic.
Data Source
AI summary
An apparatus includes a fractional divider and a modulator circuit. The fractional divider circuit may be configured to generate a feedback clock signal in response to a selection signal, a divided clock signal and an output clock signal. The modulator circuit may be configured to generate the selection signal in response to the feedback clock signal. The fractional divider may generate four phase clock signals from the divided clock signal. The four phase clock signals may be interleaved by the fractional divider circuit to select one of the four phase clock signals as the feedback clock signal. The fractional divider operates at a divide-by-4 clock speed. The selection signal may be synchronized in response to the divided clock signal to generate the feedback clock signal. The fractional divider circuit may be implemented using CMOS logic.