CMOS Divide-by-2 Circuit Using Feed-Forward and Series Peaking
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Solution Overview
Problem
Conventional CMOS divide-by-2 circuits fail to operate at 60 GHz due to short clock periods and RC delays, leading to the use of injection locked dividers with limitations such as narrow locking ranges and unproven commercial production.
Innovation Solution
A robust divide-by-2 circuit is developed by removing series bias transistors to increase headroom, incorporating series peaking inductors to eliminate RC delays, and using vector summation of orthogonal clocks to enhance the amplitude of clock signals, along with feed-forward paths regulated by current sources to adjust resonant characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional CMOS divide-by-2 circuits are used at 60 GHz, then the circuit structure is simple, but the circuit fails to operate due to short clock periods and RC delays
Solution Approach 1:
The patent changes the load impedance parameters by replacing conventional resistive loads with parallel RLC resonant circuits. This transforms the frequency response characteristics, creating a bandpass filter effect that allows the circuit to operate reliably at 60 GHz by resonating at the target frequency while suppressing other frequencies.
Solution Approach 2:
The patent substitutes the conventional RC delay mechanism with an RLC resonant system. By introducing inductors in parallel with resistors and capacitors, the circuit transitions from being limited by RC time constants to being governed by RLC resonant frequency, enabling operation at the desired 60 GHz band.
2Reliability
If injection locked dividers are used to achieve high frequency division, then the dividing function is achieved, but the locking range is very narrow and commercial production is unproven
Solution Approach 1:
The patent modifies the frequency response parameters by using parallel RLC loads with specific Q-factors and resonant frequencies. This creates a broader effective operating range compared to injection-locked dividers, as the resonant circuits provide frequency selectivity without requiring precise locking conditions.
Solution Approach 2:
The patent extracts the frequency selection function from the injection locking mechanism and implements it directly through parallel RLC resonant circuits. This eliminates the need for injection locking while maintaining frequency division capability, thereby expanding the adaptability and commercial viability.
3Ease of operation
If series bias transistors are used in the divider circuit, then the circuit provides bias control, but the headroom is reduced limiting performance
Solution Approach 1:
The patent removes series bias transistors from the signal path and replaces them with current mirrors that provide bias control from separate branches. This extraction eliminates the voltage drop across series bias devices while maintaining the ability to control operating points through current regulation.
Solution Approach 2:
The patent introduces current mirrors as intermediary devices that decouple the bias control function from the signal path. The current mirrors act as mediators that transfer bias current information without requiring series transistors in the critical signal path, thereby preserving voltage headroom.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables faster operation and improved performance of high-frequency circuits by eliminating RC delays and increasing dynamic range, allowing for reliable operation at 60 GHz without the need for injection locked dividers.
Implementation Method 1
incorporating series peaking inductors to eliminate RC delays
Implementation Method 2
feed-forward paths regulated by current sources to adjust resonant characteristics
Implementation Method 3
using vector summation of orthogonal clocks to enhance the amplitude of clock signals
Data Source
AI summary
A phase lock loop (PLL) is an important component in wireless systems. CMOS technology offers voltage controlled oscillator designs operating at 60 GHz. One of the difficulties is dividing the high frequency clock down to a manageable clock frequency using conventional CMOS. Although injection locked dividers can divide down this clock frequency, these dividers have limitations. A divide by 2 is presented that uses several techniques; feed forward, clock amplification and series peaked inductors to overcome these limitations.