CMOS Doping Process Using Single Mask for N and P Type MOSFETs
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Solution Overview
Problem
The conventional CMOS manufacturing process requires multiple masks, leading to increased manufacturing costs and reliability issues due to potential mismatching of masks, which complicates the doping processes for N-type and P-type MOSFETs.
Innovation Solution
A method is introduced where a single mask is used to form lightly-doped drain regions for both N-type and P-type MOSFETs by employing a gate stack as a hard mask, allowing for simultaneous doping of both types with a single mask, thereby reducing the number of masks needed and avoiding mismatching errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple masks are used in conventional CMOS doping processes for different MOSFET types, then doping precision can be maintained, but manufacturing cost increases and reliability decreases due to mask mismatching
Solution Approach 1:
The patent merges the doping processes for N-type and P-type MOSFETs into a single ion implantation step by using a dual-patterned mask layer. This mask layer contains both first-type doping regions and second-type doping regions in the same layer, allowing simultaneous doping of both MOSFET types without requiring separate masks, thereby eliminating mask mismatching issues while maintaining doping precision
Solution Approach 2:
The mask layer is designed to serve multiple functions: it acts as a hard mask for ion implantation, defines doping regions for both N-type and P-type MOSFETs, and controls the formation of lightly-doped drain regions. This multi-functional mask approach replaces multiple specialized masks, reducing manufacturing complexity and improving reliability
2Manufacturing precision
If multiple masks are used in conventional CMOS doping processes, then different doping regions can be precisely defined, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines multiple mask layers into a single integrated mask structure that defines all doping regions for both N-type and P-type MOSFETs. This unified mask approach maintains precise doping region definition while significantly reducing process complexity by eliminating multiple mask alignment and application steps
Solution Approach 2:
The single mask layer is segmented into different regions (first-type doping regions and second-type doping regions) that correspond to different MOSFET types. This segmentation allows precise definition of different doping regions within a single mask structure, maintaining manufacturing precision while simplifying the overall process
3Manufacturing precision
If separate doping processes are used for N-type and P-type MOSFETs, then each MOSFET type can be optimized, but manufacturing time and cost increase
Solution Approach 1:
The patent merges separate doping processes for N-type and P-type MOSFETs into a single simultaneous ion implantation process. The dual-patterned mask layer enables both doping types to occur in one step, maintaining optimization for each MOSFET type while doubling manufacturing efficiency by eliminating sequential processing steps
Solution Approach 2:
The mask layer is pre-configured with both first-type and second-type doping region patterns before the ion implantation process. This preliminary preparation allows the doping process to proceed simultaneously for both MOSFET types without requiring sequential mask changes or process steps, thereby improving productivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs and improves reliability by simplifying the doping process, allowing for precise control of doping concentrations and eliminating the need for additional ion implantation steps to adjust work functions, while maintaining the design requirements for threshold voltage.
Implementation Method 1
implanting a dopant of a first type with the first gate stack and the second gate stack as a hard mask
Implementation Method 2
Source/drain regions of the at least one type of MOSFET are then formed in the well region by ion implantation
Data Source
AI summary
The present disclosure relates to a method for manufacturing a CMOS structure. A first gate stack is formed on a semiconductor substrate in a first region. A second gate stack is formed on the semiconductor substrate in a second region. A dopant of a first type is implanted with the first gate stack and the second gate stack as a hard mask to form a lightly-doped drain region of the first type. A dopant of a second type is implanted by using a first mask and with the second gate stack as a hard mask to form a lightly-doped drain region of the second type. The first mask blocks the first region and exposes the second region. When the lightly-doped drain region of the second type is formed, the dopant of the second type over dopes a predetermined region of the lightly-doped drain region of the first type.