CMOS Transistor Double-Side Terminals Reduce Coupling Capacitance
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Solution Overview
Problem
As semiconductor technology advances and transistor devices shrink, the coupling capacitance between gate and source/drain electrodes increases, adversely affecting transistor and integrated circuit performance, with conventional techniques becoming inefficient in reducing this capacitance.
Innovation Solution
The source and drain electrodes are placed on opposite sides of the gate electrode, with corresponding terminals on the same side as the gate, reducing capacitive coupling and improving transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the source/drain electrodes and gate contact opening are disposed on the same side of the semiconductor substrate, then the device structure is simplified and manufacturing is easier, but the coupling capacitance between the gate electrode and source/drain electrodes increases
Solution Approach 1:
The patent moves the source/drain contact openings from the same side as the gate contact to the opposite side of the semiconductor substrate. This spatial reconfiguration in a different dimension (from same-plane to opposite-side arrangement) reduces the coupling capacitance between gate and source/drain electrodes while maintaining manufacturing feasibility through adjusted process sequencing.
2Productivity
If the feature size continues to shrink to improve integration density, then more transistors can be packed into smaller areas, but the coupling capacitance between gate and source/drain electrodes increases
Solution Approach 1:
By relocating source/drain contacts to the opposite side of the substrate from the gate contact, the patent creates spatial separation that reduces capacitive coupling. This dimensional reconfiguration allows continued scaling and higher integration density without proportionally increasing coupling capacitance, as the harmful electric field interaction is reduced through the substrate thickness.
3Area of stationary object
If the spacing between gate electrodes and source/drain electrodes is decreased to improve device density, then more devices can be integrated, but the coupling capacitance increases
Solution Approach 1:
The patent utilizes the vertical dimension (substrate thickness) to separate gate and source/drain contacts spatially. By placing source/drain contact openings on the opposite side from the gate contact, the effective spacing is increased in the vertical direction, reducing coupling capacitance even when lateral spacing is minimized for high density integration.
Data Source
AI summary
A transistor device includes a semiconductor substrate having a first surface and a second surface opposite the first surface, a gate structure disposed on the first surface and configured to form a channel region, and source and drain regions disposed on opposite sides of the channel region. The device also includes a source terminal and a drain terminal disposed on the second surface. The source and drain terminals are connected to the respective source and drain regions. The transistor device further include a body terminal disposed on the second surface and configured to connect the highest or lowest voltage supply to the semiconductor substrate.